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61. 发明申请

US20130001746A1 MULTI-FINGER CAPACITOR WITH REDUCED SERIES RESISTANCE 审中-公开
标题翻译：多指针电容器具有降低的串联电阻
公开(公告)号：US20130001746A1
公开(公告)日：2013-01-03
申请号：US13175554
申请日：2011-07-01
申请人： DARVIN RENNE EDWARDS
发明人： DARVIN RENNE EDWARDS
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91 , H01L28/82 , H01L28/87
摘要： An electronic die includes a multi-finger capacitor including a first electrically conductive plate including a plurality of first metal fingers joined together by a first metal base, and a second electrically conductive plate including a plurality of second metal fingers joined together by a second metal base. A dielectric layer is between the first electrically conductive plate and the second electrically conductive plate for electrically isolation. The plurality of first metal fingers and plurality of second metal fingers are interleaved with one another. The die can include a first portion that includes the multi-finger capacitor and a second portion that includes active circuitry configured to provide at least one circuit function, wherein the first and second electrically conductive plates are coupled to the active circuitry.
摘要翻译：电子管芯包括多指电容器，该多指电容器包括第一导电板，该第一导电板包括由第一金属基底连接在一起的多个第一金属指，以及包括多个第二金属指的第二导电板，第二金属指通过第二金属基底。电介质层位于第一导电板和第二导电板之间，用于电隔离。多个第一金属指和多个第二金属指彼此交错。管芯可以包括包括多指电容器的第一部分和包括被配置为提供至少一个电路功能的有源电路的第二部分，其中第一和第二导电板耦合到有源电路。

62. 发明申请

US20120326273A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20120326273A1
公开(公告)日：2012-12-27
申请号：US13606673
申请日：2012-09-07
申请人： Satoru Mihara
发明人： Satoru Mihara
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01L27/11507 , H01L27/11509
摘要： A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.
摘要翻译：一种制造包括多个电容器的半导体器件的方法，每个电容器具有底部电极，电介质层和顶部电极，包括堆叠底部电极层，电介质层和顶部电极层，图案化顶部电极层以形成多个形成覆盖多个顶部电极并使多个顶部电极的布置的最外侧顶部电极的端部露出的掩模图案，并且使用掩模图案对介电层进行图案化的掩模图案。

63. 发明申请

US20120319239A1 SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US20120319239A1
公开(公告)日：2012-12-20
申请号：US13161076
申请日：2011-06-15
申请人： Chun Hua CHANG , Sung-Hui HUANG , Der-Chyang YEH
发明人： Chun Hua CHANG , Sung-Hui HUANG , Der-Chyang YEH
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A first etch stop layer is disposed over the TSV structure. A first dielectric layer is disposed in contact with the first etch stop layer. A first conductive structure is disposed through the first etch stop layer and the first dielectric layer. The first conductive structure is electrically coupled with the TSV structure. The TSV structure is substantially wider than the first conductive structure. A second etch stop layer is disposed in contact with the first dielectric layer. A metal-insulator-metal (MIM) capacitor structure is disposed in contact with the second etch stop layer.
摘要翻译：半导体结构包括设置在基板中的贯通基板通孔（TSV）结构。第一蚀刻停止层设置在TSV结构上。第一介电层设置成与第一蚀刻停止层接触。通过第一蚀刻停止层和第一介电层设置第一导电结构。第一导电结构与TSV结构电耦合。 TSV结构基本上比第一导电结构宽。第二蚀刻停止层设置成与第一介电层接触。金属 - 绝缘体 - 金属（MIM）电容器结构设置成与第二蚀刻停止层接触。

64. 发明申请

US20120306018A1 BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH 有权
标题翻译：包含有效装置的BEOL结构和机械强度
公开(公告)号：US20120306018A1
公开(公告)日：2012-12-06
申请号：US13149797
申请日：2011-05-31
申请人： Stephen M. Gates , Daniel C. Edelstein , Satyanarayana V. Nitta
发明人： Stephen M. Gates , Daniel C. Edelstein , Satyanarayana V. Nitta
IPC分类号： H01L29/772 , H01L29/92 , H01L21/20 , H01L29/02
CPC分类号： H01L23/481 , H01L21/02667 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/5228 , H01L23/53238 , H01L24/80 , H01L25/18 , H01L25/50 , H01L27/016 , H01L27/0688 , H01L29/66984 , H01L29/861 , H01L29/872 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/00
摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.
摘要翻译：单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。半导体器件层没有与衬底接合或结合界面。使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

65. 发明申请

US20120256193A1 MONOLITHIC INTEGRATED CAPACITORS FOR HIGH-EFFICIENCY POWER CONVERTERS 审中-公开
标题翻译：用于高效电力转换器的单片集成电容器
公开(公告)号：US20120256193A1
公开(公告)日：2012-10-11
申请号：US13165396
申请日：2011-06-21
申请人： Francois Hebert , Stephen J. Gaul , Shea Petricek
发明人： Francois Hebert , Stephen J. Gaul , Shea Petricek
IPC分类号： H01L29/02 , H01L29/06 , H01L21/02 , H01L29/92
CPC分类号： H01L23/5223 , H01L21/823418 , H01L23/3107 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/0629 , H01L27/088 , H01L28/60 , H01L29/402 , H01L29/4175 , H01L29/42368 , H01L29/456 , H01L29/7813 , H01L29/7835 , H01L2224/04042 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/73265 , H01L2924/00014 , H01L2924/01322 , H01L2924/13091 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2924/00011 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer. The integrated capacitor comprises a first bottom electrode that includes the portion of the first metal layer, a second bottom electrode that includes the portion of the second metal layer, the dielectric layer over the portions of the first and second metal layers, and a top electrode that includes the top metal layer over the dielectric layer.
摘要翻译：提供了诸如具有集成电容器的功率转换器的半导体结构，并且包括半导体衬底，在第一位置处的衬底上的高侧输出功率器件和在第二位置处的衬底上的低侧输出功率器件位置与第一个位置相邻。第一金属层位于高侧输出功率器件的上方并且电耦合到高侧输出功率器件，并且第二金属层在低侧输出功率器件的上方并且电耦合到低侧输出功率器件。电介质层位于第一金属层的一部分和第二金属层的一部分上，并且顶部金属层在电介质层的上方。集成电容器包括包括第一金属层的部分的第一底部电极，包括第二金属层的部分的第二底部电极，第一和第二金属层的部分上的电介质层，以及顶部电极其包括在电介质层上的顶部金属层。

66. 发明申请

US20120217615A1 GRAIN BOUNDARY-INSULATED SEMICONDUCTOR CERAMIC, SEMICONDUCTOR CERAMIC CAPACITOR, AND METHOD FOR PRODUCING SEMICONDUCTOR CERAMIC CAPACITOR 有权
标题翻译：晶界绝缘半导体陶瓷，半导体陶瓷电容器及生产半导体陶瓷电容器的方法
公开(公告)号：US20120217615A1
公开(公告)日：2012-08-30
申请号：US13358732
申请日：2012-01-26
申请人： Tsutomu Tatekawa
发明人： Tsutomu Tatekawa
IPC分类号： H01L29/92 , H01L21/02 , H01B1/04
CPC分类号： H01G4/1227 , C03C3/087 , C03C14/004 , C03C2214/20 , C04B35/47 , C04B2235/3208 , C04B2235/3225 , C04B2235/3281 , C04B2235/3298 , C04B2235/36 , C04B2235/652 , C04B2235/6582 , C04B2235/6587 , C04B2235/72 , C04B2235/768 , C04B2235/85 , H01G4/1281 , H01G4/129
摘要： A grain boundary-insulated semiconductor ceramic contains a SrTiO3-based compound as a main component, and a diffusing agent containing a grain boundary insulating agent and a glass component. The grain boundary insulating agent is composed of a material free of lead, the glass component mainly contains a SiO2—X2O-MO—TiO2-based glass material that does not contain boron or lead and in which X represents an alkali metal, and M represents at least one of barium, strontium, and calcium, and the content of the glass component is 3 to 15 parts by weight relative to 100 parts by weight of the grain boundary insulating agent. A component base is composed of the grain boundary-insulated semiconductor ceramic.
摘要翻译：晶界绝缘半导体陶瓷含有SrTiO 3系化合物作为主要成分，含有晶界绝缘剂和玻璃成分的扩散剂。晶界绝缘剂由不含铅的材料构成，玻璃成分主要含有不含硼或铅的SiO 2-X 2 O-MO-TiO 2系玻璃材料，X表示碱金属，M表示钡，锶，钙中的至少一种，相对于100重量份的晶界绝缘剂，玻璃成分的含量为3〜15重量份。元件基底由晶界绝缘半导体陶瓷组成。

67. 发明申请

US20120199947A1 METHOD FOR MANUFACTURING AND REOXIDIZING A TIN/TA2O5/TIN CAPACITOR 有权
标题翻译：用于制造和再氧化TIN / TA2O5 / TIN电容器的方法
公开(公告)号：US20120199947A1
公开(公告)日：2012-08-09
申请号：US13364823
申请日：2012-02-02
申请人： Mickael Gros-Jean
发明人： Mickael Gros-Jean
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L21/02274 , C23C16/405 , C23C16/45542 , H01L21/02183 , H01L21/0228 , H01L21/0234 , H01L21/3105 , H01L28/40
摘要： A method for manufacturing a TiN/Ta2O5/TiN capacitor, including the steps of forming a Ta2O5 layer on a TiN support by a plasma-enhanced atomic layer deposition method, or PEALD; and submitting the obtained structure to an N2O plasma for a duration sufficient to oxidize the Ta2O5 layer without oxidizing the TiN support.
摘要翻译：一种制造TiN / Ta 2 O 5 / TiN电容器的方法，包括以下步骤：通过等离子体增强原子层沉积方法在TiN载体上形成Ta 2 O 5层;或PEALD; 并将获得的结构提供到N 2 O等离子体持续足以氧化Ta 2 O 5层的持续时间，而不氧化TiN载体。

68. 发明申请

US20120193632A1 SILICON STRUCTURE AND MANUFACTURING METHODS THEREOF AND OF CAPACITOR INCLUDING SILICON STRUCTURE 有权
标题翻译：其结构及其制造方法及电容器，包括硅结构
公开(公告)号：US20120193632A1
公开(公告)日：2012-08-02
申请号：US13357040
申请日：2012-01-24
申请人： Satoshi TORIUMI
发明人： Satoshi TORIUMI
IPC分类号： H01L29/94 , H01L21/205 , H01L29/04 , H01L29/92 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L28/84 , H01L29/94 , H01L29/945
摘要： Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.
摘要翻译：提供具有三维复杂形状的硅结构。进一步提供一种使用自发形成有序图形以形成纳米结构的现象制造硅结构的简单和容易的方法。在氢气氛下对非晶硅层进行等离子体处理，同时进行以下工序：在硅层的表面生长微晶硅的反应工序和暴露于非晶硅层的非晶硅层的反应工序，从而形成在硅层上形成包含微结晶状态的上部结构和非晶态的下部结构的纳米结构体; 因此，可以提供具有三维复杂形状的硅结构。

69. 发明申请

US20120146184A1 TWO TERMINAL MEMCAPACITOR DEVICE 有权
标题翻译：两端终端设备
公开(公告)号：US20120146184A1
公开(公告)日：2012-06-14
申请号：US13383981
申请日：2009-08-28
申请人： Matthew Pickett , Julien Borghetti , Jianhua Yang
发明人： Matthew Pickett , Julien Borghetti , Jianhua Yang
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： G11C11/24 , H01G7/06 , H01L27/101 , H01L28/40 , H01L29/167 , H01L29/93
摘要： A memcapacitor device includes a memcapacitive matrix interposed between a first electrode and a second electrode. The memcapacitive matrix includes deep level dopants having a first decay time constant and shallow level dopants having a second decay time constant. The second decay time constant is substantially shorter than the first decay time constant. The capacitance of the memcapacitor device depends upon an initial voltage applied across the memcapacitive matrix and a time dependent change in capacitance of the memcapacitor device depends upon the first decay time constant. A method for forming a memcapacitive device is also provided.
摘要翻译：电容器装置包括插入在第一电极和第二电极之间的存储电容矩阵。电容矩阵包括具有第一衰减时间常数的深层掺杂剂和具有第二衰减时间常数的浅层掺杂剂。第二衰减时间常数明显短于第一衰减时间常数。存储器件器件的电容取决于施加在存储电容矩阵上的初始电压，并且存储器件器件的时间相关的电容变化取决于第一衰减时间常数。还提供了一种用于形成电容器件的方法。

70. 发明申请

US20120146182A1 HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS 有权
标题翻译：高密度三维集成电容器
公开(公告)号：US20120146182A1
公开(公告)日：2012-06-14
申请号：US12964049
申请日：2010-12-09
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/91 , H01L23/481 , H01L28/40 , H01L28/60 , H01L2223/6622 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
摘要翻译：组件包括基板和形成为与基板接触的电容器。基底可以由具有小于10ppm /℃的热膨胀系数的材料组成。基底可以具有从其向下延伸的表面和开口。电容器可以包括至少第一和第二对导电板以及第一和第二电极。第一和第二对板可以与相应的第一和第二电位连接。第一和第二对板可以沿着开口的内表面延伸，每个板通过电介质层与至少一个相邻的板分离。第一和第二电极可以暴露在基板的表面，并且可以耦合到相应的第一和第二对板。

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