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61. 发明授权

US08981854B2 Clock distributor and electronic apparatus 有权
标题翻译：时钟分配器和电子设备
公开(公告)号：US08981854B2
公开(公告)日：2015-03-17
申请号：US13875837
申请日：2013-05-02
申请人： Fujitsu Limited
发明人： Yasumoto Tomita , Hirotaka Tamura
IPC分类号： H03L7/099 , H03L7/24 , G06F1/10 , H03L7/18 , H03L7/07 , H03L7/08
CPC分类号： H03L7/18 , G06F1/10 , H03L7/07 , H03L7/0805 , H03L7/099 , H03L7/24
摘要： A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.
摘要翻译：时钟分配器包括第一振荡器和第二振荡器，每个振荡器和第二振荡器输入控制振荡频率的信号，并输入其中一个时钟; 连接第一振荡器和第二振荡器的布线部分; 第一转换元件，其将来自第一振荡器的输出转换为电流，并将结果输出到连接到布线部分的第一连接部分; 第二转换元件，将第一连接部分的电压转换为电流，并将结果输出到第一振荡器; 第三转换元件，其将来自第二振荡器的输出转换为电流，并将结果输出到连接到布线部分的第二连接部分; 以及第四转换元件，其将第二连接部分的电压转换为电流，并将结果输出到第二振荡器。

62. 发明授权

US08948332B2 Method of static phase offset correction for a linear phase detector 有权
标题翻译：线性相位检测器的静态相位偏移校正方法
公开(公告)号：US08948332B2
公开(公告)日：2015-02-03
申请号：US13679884
申请日：2012-11-16
申请人： John Kenney , Jeremy Z. Walker
发明人： John Kenney , Jeremy Z. Walker
IPC分类号： H03D3/24 , H03L7/07 , G01R25/00
CPC分类号： H03L7/07 , G01R25/005 , H03L9/00
摘要： A method for calibrating a clock and data recovery circuit may include configuring a phase detector as a bang-bang phase detector. The bang-bang phase detector may be used to determine a phase difference between a sampling clock provided by an interpolator and a calibration signal. The phase detector may also be configured as a linear phase detector. While using the linear phase detector, a linear phase detector parameter may be adjusted such that the phase difference between the calibration signal and the sampling clock is zero, while keeping the phase of the sampling clock fixed.
摘要翻译：用于校准时钟和数据恢复电路的方法可以包括将相位检测器配置为爆炸相位检测器。爆轰相位检测器可用于确定由内插器提供的采样时钟与校准信号之间的相位差。相位检测器也可以被配置为线性相位检测器。在使用线性相位检测器时，可以调节线性相位检测器参数，使得校准信号和采样时钟之间的相位差为零，同时保持采样时钟的相位固定。

63. 发明授权

US08923467B2 Clock and data recovery using receiver clock spread spectrum modulation and offset compensation 有权
标题翻译：使用接收机时钟扩频调制和偏移补偿的时钟和数据恢复
公开(公告)号：US08923467B2
公开(公告)日：2014-12-30
申请号：US13674812
申请日：2012-11-12
申请人： Rambus Inc.
发明人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
IPC分类号： H03D3/24 , H04L7/00 , H04L7/033 , H03L7/093 , H03L7/07
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.
摘要翻译：一种用于执行时钟和数据恢复的系统和方法。根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。

64. 发明授权

US08884671B2 Phase-locked loop system and operation 有权
标题翻译：锁相环系统和操作
公开(公告)号：US08884671B2
公开(公告)日：2014-11-11
申请号：US14251228
申请日：2014-04-11
申请人： Synopsys, Inc.
发明人： Jan Grabinski
IPC分类号： H03L7/087 , H03L7/07
CPC分类号： H03L7/087 , H03L7/10 , H03L7/101
摘要： A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.
摘要翻译：锁相环系统具有受控振荡器，其基于振荡器控制信号提供输出时钟信号，反馈路径被配置为基于输出时钟信号提供反馈信号;相位检测器，被配置为提供基于相位的相关信号在反馈信号和参考时钟信号上，相位评估块，被配置为基于相位相关信号提供振荡器控制信号;频率检测器，其确定输出时钟信号和参考时钟信号之间的频率比是否具有期望的值和控制逻辑。控制逻辑被配置为在启动周期期间在确定频率比的期望值时禁用相位评估块; 在禁止相位评估块之后，检测参考时钟信号的后续时钟沿; 并且响应于后续时钟沿的检测使能相位评估块。

65. 发明授权

US08878993B2 Image data processing apparatus 有权
标题翻译：图像数据处理装置
公开(公告)号：US08878993B2
公开(公告)日：2014-11-04
申请号：US11980476
申请日：2007-10-31
申请人： Yoshinori Asamura
发明人： Yoshinori Asamura
IPC分类号： H03L7/00 , H04N5/04 , G09G5/00 , H03L7/07 , G09G5/12
CPC分类号： H03L7/07 , G09G5/008 , G09G5/12
摘要： An image data processing apparatus of the present invention includes: a base clock output circuit for outputting a base clock; a plurality of image processors; and a plurality of external PLL circuits provided for each one of the plurality of image processors. The plurality of external PLL circuits each synchronize an output clock given from a corresponding one of the plurality of image processors with the base clock.
摘要翻译：本发明的图像数据处理装置包括：基本时钟输出电路，用于输出基本时钟; 多个图像处理器; 以及为所述多个图像处理器中的每一个设置的多个外部PLL电路。多个外部PLL电路各自使得从多个图像处理器中的对应的一个图像处理器给出的输出时钟与基准时钟同步。

66. 发明授权

US08866556B2 Phase shift phase locked loop 有权
标题翻译：相移锁相环
公开(公告)号：US08866556B2
公开(公告)日：2014-10-21
申请号：US12395209
申请日：2009-02-27
申请人： Alan C. Rogers
发明人： Alan C. Rogers
IPC分类号： H03L7/085 , H03L7/089 , H03L7/081 , H03L7/087 , H03L7/07 , H04J3/06
CPC分类号： H03L7/081 , H03L7/07 , H03L7/087 , H04J3/0685 , H04L7/0037
摘要： A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.
摘要翻译：描述了相移锁相环（PSPLL）。相移PLL包括耦合到PLL的输入的PLL和相位调整电路。相位调整电路具有第一输入，第一输出，第二输入，第三输入和第二输出。第一输出和第二输出分别耦合到PLL的第一输入和第二输入。相位调整电路的第二输入端接收反馈信号，相位调整电路的第三输入端接收控制信号。相位调整电路接收参考信号，并将基于参考信号的第一输出信号和第二输出信号发送到PLL，以便以小于输出信号的时间周期的增量调整PLL的输出信号的相位的PLL。

67. 发明申请

US20140306741A1 Phase-Locked Loop System and Operation 有权
标题翻译：锁相环系统和操作
公开(公告)号：US20140306741A1
公开(公告)日：2014-10-16
申请号：US14251228
申请日：2014-04-11
申请人： Synopsys, Inc.
发明人： Jan Grabinski
IPC分类号： H03L7/07
CPC分类号： H03L7/087 , H03L7/10 , H03L7/101
摘要： A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.
摘要翻译：锁相环系统具有受控振荡器，其基于振荡器控制信号提供输出时钟信号，反馈路径被配置为基于输出时钟信号提供反馈信号;相位检测器，被配置为提供基于相位的相关信号在反馈信号和参考时钟信号上，相位评估块，被配置为基于相位相关信号提供振荡器控制信号;频率检测器，其确定输出时钟信号和参考时钟信号之间的频率比是否具有期望的值和控制逻辑。控制逻辑被配置为在启动周期期间在确定频率比的期望值时禁用相位评估块; 在禁止相位评估块之后，检测参考时钟信号的后续时钟沿; 并且响应于后续时钟沿的检测使能相位评估块。

68. 发明申请

US20110148484A1 PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER 有权
标题翻译：相位锁定频率合成器
公开(公告)号：US20110148484A1
公开(公告)日：2011-06-23
申请号：US12645434
申请日：2009-12-22
申请人： Helen H. Kim , Matthew D. Cross , Merlin R. Green , Daniel D. Santiago
发明人： Helen H. Kim , Matthew D. Cross , Merlin R. Green , Daniel D. Santiago
IPC分类号： H03L7/085 , H03L7/07
CPC分类号： H03L7/23 , H03L7/099
摘要： Described is a frequency synthesizer having a wide output frequency range and small frequency tuning steps. In-band spurious components are maintained at low levels and phase noise is significantly reduced. The frequency synthesizer can be fabricated as an integrated circuit device having a small area and low power dissipation. The frequency synthesizer can be used in wideband frequency systems to reduce cost and size by replacing multiple frequency synthesizers each devoted to a portion of the overall system frequency range.
摘要翻译：描述了具有宽输出频率范围和小频率调谐步骤的频率合成器。带内杂散分量保持在低电平，相位噪声明显降低。频率合成器可以制造成具有小面积和低功耗的集成电路器件。频率合成器可以用于宽带频率系统，通过替换每个专用于整个系统频率范围的一部分的多个频率合成器来降低成本和尺寸。

69. 发明申请

US20080204093A1 Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal 有权
标题翻译：使用双边相位检测的占空比校正的多相发生器和用于产生多相信号的方法
公开(公告)号：US20080204093A1
公开(公告)日：2008-08-28
申请号：US11712162
申请日：2007-02-28
申请人： Feng Lin , Roman Andreas Royer
发明人： Feng Lin , Roman Andreas Royer
IPC分类号： H03H11/26 , H03L7/07
CPC分类号： G06F1/10 , H03K5/133 , H03L7/0805 , H03L7/0812 , H03L7/085
摘要： Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.
摘要翻译：这里通常描述具有占空比校正的多相发生器的实施例。在一些实施例中，多相发生器包括串联布置的可控延迟级和双边缘相位检测器电路。双边缘相位检测器电路可以产生控制信号，以基于由延迟级操作的相同状态信号的相应上升沿和相应的下降沿来调整由延迟级提供的延迟。描述其他电路，系统和方法。

70. 发明申请

US20080174350A1 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US20080174350A1
公开(公告)日：2008-07-24
申请号：US11826401
申请日：2007-07-16
申请人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
发明人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/08 , H03K5/14 , H03L7/07
CPC分类号： H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00065 , H03L7/0814 , H03L7/087
摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。校正控制单元响应于占空比检测信号产生校正控制信号。占空比校正单元校正内部的占空比。响应于校正控制信号，从而输出参考时钟。

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