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61. 发明授权

US10135567B2 Systems and methods for advanced iterative decoding and channel estimation of concatenated coding systems 有权
公开(公告)号：US10135567B2
公开(公告)日：2018-11-20
申请号：US15236066
申请日：2016-08-12
申请人： LN2 DB, LLC
发明人： Branimir R Vojcic , Farnaz Shayegh , Hakan Dogan , Wookwon Lee
IPC分类号： H04L27/28 , H04L1/00 , G06F11/16 , H04L25/02 , H03M13/11 , H03M13/15 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/37 , H03M13/00 , H04L27/26 , H04B17/309 , H03M13/23 , H03M13/45 , H03M13/09 , H03M13/39
摘要： Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.

62. 发明授权

US10110253B2 Receiver 有权
公开(公告)号：US10110253B2
公开(公告)日：2018-10-23
申请号：US15125870
申请日：2015-03-03
申请人： Hitachi Kokusai Electric Inc.
发明人： Keisuke Yamamoto
IPC分类号： H03M13/27 , H03M13/37 , H03M13/45 , H04L1/00 , H03M13/25 , H03M13/29 , H03M13/00 , H04B7/0413
摘要： Provided is a BICM-ID technique which suppresses deterioration of decoding characteristics and reduces a calculation amount. A receiver includes a demodulator, deinterleaver, decoder, and interleaver. The demodulator outputs first extrinsic information by using a received signal encoded and interleaved and a priori information. The deinterleaver processes the first extrinsic information and outputs second extrinsic information. The decoder outputs third extrinsic information by using the second extrinsic information. The interleaver processes the third extrinsic information and outputs fourth extrinsic information. In the receiver that performs iterative decoding processing using the fourth extrinsic information as the a priori information, the demodulator includes a generator, a received signal point candidate narrowing-down unit, and a likelihood calculation unit. The generator generates a plurality of received signal point candidates. The likelihood calculation unit creates the first extrinsic information based on the narrowed-down received signal point candidates, the a priori information, and the received signal.

63. 发明授权

US10073734B2 Flash memory read error recovery with soft-decision decode 有权
公开(公告)号：US10073734B2
公开(公告)日：2018-09-11
申请号：US14697904
申请日：2015-04-28
申请人： Seagate Technology LLC
发明人： Erich F. Haratsch , Jeremy Werner , Zhengang Chen , Earl T. Cohen , Yunxiang Wu , Ning Chen
IPC分类号： G11C29/00 , G06F11/10 , H03M13/37 , H03M13/00 , G11C29/52 , H03M13/45 , H03M13/11 , H03M13/39 , H03M13/41
CPC分类号： G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3905 , H03M13/41 , H03M13/45 , H03M13/6561
摘要： An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.

64. 发明授权

US10055293B2 High performance memory controller 有权
公开(公告)号：US10055293B2
公开(公告)日：2018-08-21
申请号：US15583678
申请日：2017-05-01
申请人： Micron Technology, Inc.
发明人： Violante Moschiano , Walter Di Francesco , Luca De Santis , Giovanni Santin
IPC分类号： G11C29/00 , G06F11/10 , H03M13/37 , G11C29/02 , G11C29/52 , H03M13/11 , G11C29/04 , H03M13/45
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/1076 , G11C29/02 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/2906 , H03M13/3715 , H03M13/45
摘要： A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

65. 发明授权

US10050644B2 Receiver, wireless communication system, and wireless communication method 有权
公开(公告)号：US10050644B2
公开(公告)日：2018-08-14
申请号：US15561806
申请日：2016-02-19
申请人： Hitachi Kokusai Electric Inc.
发明人： Keisuke Yamamoto , Takashi Yano
IPC分类号： H03M7/00 , H03M13/27 , H03M13/45 , H03M13/01 , H04L1/00 , H01Q1/00
摘要： A wireless communication technique in which information that has been encoded and interleaved (the sequence of bits has been rearranged) on the transmission side is subjected to iterative decoding processing by using a demodulator, a deinterleaver, a decoder, and an interleaver on the receiving side.

66. 发明申请

US20180203625A1 STORAGE SYSTEM WITH MULTI-DIMENSIONAL DATA PROTECTION MECHANISM AND METHOD OF OPERATION THEREOF 审中-公开
公开(公告)号：US20180203625A1
公开(公告)日：2018-07-19
申请号：US15410528
申请日：2017-01-19
申请人： CNEX LABS, Inc.
发明人： Xiaojie Zhang , Pengfei Huang
IPC分类号： G06F3/06 , H03M13/45 , H03M13/00
CPC分类号： G06F3/0622 , G06F3/0619 , G06F3/064 , G06F3/0683 , H03M13/152 , H03M13/2909 , H03M13/2927 , H03M13/45 , H03M13/611
摘要： A storage system includes: a data storage system, configured to: load a user data block in a user data array, and link a column protection and a row protection with the user data array; and a non-volatile storage device, coupled to the data storage system, configured to store the user data block linked to the column protection and the row protection.

67. 发明申请

US20180143875A1 MONITORING ERROR CORRECTION OPERATIONS PERFORMED IN MEMORY 审中-公开
公开(公告)号：US20180143875A1
公开(公告)日：2018-05-24
申请号：US15873024
申请日：2018-01-17
申请人： Micron Technology, Inc.
发明人： Mustafa N. Kaynak , Patrick R. Khayat , Sivagnanam Parthasarathy
IPC分类号： G06F11/10 , H03M13/45 , G11C16/26 , G11C29/52
CPC分类号： G11C16/26 , G06F11/1012 , G11C16/0483 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/1111 , H03M13/13 , H03M13/3738 , H03M13/45
摘要： The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.

68. 发明申请

US20180131393A1 RECEIVER, WIRELESS COMMUNICATION SYSTEM, AND WIRELESS COMMUNICATION METHOD 审中-公开
公开(公告)号：US20180131393A1
公开(公告)日：2018-05-10
申请号：US15561806
申请日：2016-02-19
申请人： Hitachi Kokusai Electric Inc.
发明人： Keisuke YAMAMOTO , Takashi YANO
IPC分类号： H03M13/27 , H03M13/45 , H04L1/00 , H03M13/01
CPC分类号： H03M13/2796 , H01Q1/00 , H03M13/015 , H03M13/27 , H03M13/45 , H04L1/00 , H04L1/005
摘要： A wireless communication technique in which information that has been encoded and interleaved (the sequence of bits has been rearranged) on the transmission side is subjected to iterative decoding processing by using a demodulator, a deinterleaver, a decoder, and an interleaver on the receiving side.

69. 发明申请

US20180076832A1 MEMORY SYSTEM THAT CARRIES OUT SOFT BIT DECODING 审中-公开
公开(公告)号：US20180076832A1
公开(公告)日：2018-03-15
申请号：US15446938
申请日：2017-03-01
申请人： Toshiba Memory Corporation
发明人： Takuya HAGA
IPC分类号： H03M13/45 , G11C16/34 , G11C16/26 , G11C16/14 , G06F11/10 , G11C29/52
CPC分类号： H03M13/458 , G06F11/1012 , G06F11/1068 , G11C11/5642 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/349 , G11C29/52 , G11C2029/0411 , H03M13/1111 , H03M13/45 , H03M13/6325
摘要： A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.

70. 发明申请

US20180054278A1 REDUCED-STAGE POLAR DECODING 审中-公开
公开(公告)号：US20180054278A1
公开(公告)日：2018-02-22
申请号：US15651390
申请日：2017-07-17
申请人： WUXIAN SHI , YIQUN GE
发明人： WUXIAN SHI , YIQUN GE
IPC分类号： H04L1/00 , H03M13/45
CPC分类号： H04L1/0058 , H03M13/13 , H03M13/45 , H03M13/6502 , H03M13/6505 , H04L1/0045 , H04L1/0052 , H04W88/02 , H04W88/08
摘要： In reduced-stage polar decoding, a received word that is based on an N-bit codeword of a polar code is decoded using fewer than log2N Log Likelihood Ratio (LLR) stages. Decoding uses a reduced stage decoding configuration. In an embodiment, such a configuration includes at least one higher-order LLR stage with nodes implementing functions that are based on a combination of lower-order polar code kernels.

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