专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20060005098A1 Interface workbench for high volume data buffering and connectivity 有权
公开(公告)号：US20060005098A1
公开(公告)日：2006-01-05
申请号：US11028294
申请日：2005-01-04
申请人： Marcus Lotz , Andreas Guldner
发明人： Marcus Lotz , Andreas Guldner
IPC分类号： G06F15/00 , H04L1/00 , G06F15/76 , G06F11/00 , G06F11/30 , H03M13/00 , G08C25/00 , G11C29/00
CPC分类号： H04L1/1835 , H04L1/0082
摘要： The application is directed to the accurate transfer of data. In various methods, systems, and devices of the present invention, a connectivity workbench may be employed to correct errors in data records transmitted between two systems. This workbench may enable real-time manual fixes as well as previously selected automatic fixes. A method that embodies the invention may include receiving a data record, verifying whether or not the data record is error free, correcting the data record and then buffering it until it is needed at a downstream system. In some embodiments, if the downstream system is busy when it receives the data record or if the target location is otherwise occupied, the data record may be returned to the upstream system and then resent at a later time once the error is resolved.

62. 发明申请

US20050283700A1 Digital error mapping circuit and method 审中-公开
标题翻译：数字误差映射电路及方法
公开(公告)号：US20050283700A1
公开(公告)日：2005-12-22
申请号：US11211830
申请日：2005-08-25
申请人： James O'Dea
发明人： James O'Dea
IPC分类号： G11B20/18 , H04L1/00 , G06F11/00 , G06F11/30 , G08C25/00 , G11C29/00 , H03M13/00
CPC分类号： G11B20/1833
摘要： A method and apparatus for detecting and mapping digital errors on optical media is provided which includes an invalid symbol detector capable of detecting errors in real time. The method and apparatus further includes the ability to set a run-length mask enabling selective display of specific run-lengths. The method and apparatus of error mapping enables the detection of errors at the time that the data is read and before the data is processed by traditional error detection and correction circuits. Capturing the errors relative to their physical location on the optical media allows the creation of an error map or surface presentation of the errors. The resulting error map displays the location and magnitude of digital errors caused by invalid symbols. The error map allows the test operator to quickly determine the specific location and or distribution of errors on the optical media.
摘要翻译：提供了一种用于检测和映射光学介质上的数字错误的方法和装置，其包括能够实时检测错误的无效符号检测器。该方法和装置还包括设置能够选择性地显示特定游程长度的游程长度掩码的能力。错误映射的方法和装置能够在数据被读取时和传统的错误检测和校正电路处理数据之前检测错误。捕获相对于其在光学介质上的物理位置的错误允许创建错误图或错误的表面呈现。所产生的错误图显示由无效符号引起的数字错误的位置和幅度。错误图允许测试操作员快速确定光学介质上的错误的具体位置和/或分布。

63. 发明申请

US20050283699A1 Map error information obtaining system and map error information obtaining method 有权
标题翻译：地图错误信息获取系统和地图错误信息获取方法
公开(公告)号：US20050283699A1
公开(公告)日：2005-12-22
申请号：US10872704
申请日：2004-06-21
申请人： Kimihiro Nomura , Hitoshi Araki , Keiichi Senda , Masato Yuda , Yoshiteru Kawasaki , Tadashi Yoshida
发明人： Kimihiro Nomura , Hitoshi Araki , Keiichi Senda , Masato Yuda , Yoshiteru Kawasaki , Tadashi Yoshida
IPC分类号： G01C21/32 , G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G01C21/32
摘要： The present invention provides a map error information obtaining system which can promote the collection of the map error information as well as reduce the number of man-hours required for researching the site and verifying whether or not the collected map error information is accurate. The map error information obtaining system herein disclosed comprises a position detecting apparatus including image obtaining means for obtaining image data indicative of an actual condition of and in the vicinity of a current position, and a center apparatus, the position detecting apparatus being operative to transmit map error information including a position of the map information and image data where it is judged that there is a difference, to the center apparatus. The center apparatus is operative to correct the map information after verifying whether or not the difference in the map information is accurate using the image data. Furthermore, the center apparatus is operative to calculate an evaluation point for each of the position detecting apparatuses which have transmitted the map error information so that operators operating the position detecting apparatuses can be rewarded in accordance with their evaluation points.
摘要翻译：本发明提供一种地图错误信息获取系统，其可以促进地图错误信息的收集，并且减少研究站点所需的工作人员数量，并验证所收集的地图错误信息是否准确。本文公开的地图误差信息获取系统包括：位置检测装置，包括用于获取指示当前位置的实际状况和附近的图像数据的图像获取装置;以及中心装置，位置检测装置可操作以发送地图将包括地图信息的位置和判定有差异的图像数据的错误信息提供给中心装置。在使用图像数据验证地图信息的差异是否准确之后，中心装置可操作地校正地图信息。此外，中心装置用于计算已经发送了地图误差信息的每个位置检测装置的评估点，使得操作位置检测装置的操作者可以根据其评估点得到奖励。

64. 发明授权

US06978412B1 Method and apparatus for adaptive frame tracking 有权
标题翻译：自适应帧跟踪的方法和装置
公开(公告)号：US06978412B1
公开(公告)日：2005-12-20
申请号：US09375120
申请日：1999-08-16
申请人： Daniel B. Reents , Patrick Maupin
发明人： Daniel B. Reents , Patrick Maupin
IPC分类号： H04L1/00 , G08C25/00 , H03M13/00
CPC分类号： H04L1/0002
摘要： The present invention provides for an apparatus and a method for performing adaptive frame tracking. The present invention comprises an adaptive frame tracking unit capable of receiving and sending at least one data packet and automatically adjusting a data rate of the data packet by determining if there exists at least one data frame error and correcting for the data frame error in response to a determination that there exists at least one the data frame error.
摘要翻译：本发明提供一种用于执行自适应帧跟踪的装置和方法。本发明包括一种自适应帧跟踪单元，其能够接收和发送至少一个数据分组，并且通过确定是否存在至少一个数据帧错误并且响应于所述数据帧错误来校正数据帧错误来自动调整数据分组的数据速率确定存在至少一个数据帧错误。

65. 发明申请

US20050278600A1 Memory size allocation device and method applying in interleaving 有权
标题翻译：内存大小分配装置和方法应用于交织
公开(公告)号：US20050278600A1
公开(公告)日：2005-12-15
申请号：US11028545
申请日：2005-01-05
申请人： Alex Chang , Aaron Wang
发明人： Alex Chang , Aaron Wang
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , G11C29/00 , H03M13/00 , H03M13/27 , H04L1/00
CPC分类号： H03M13/2782 , H03M13/2732
摘要： A method and device for interleaving the (N+1) input data and for allocating the corresponding memory comprises the steps of allocating a mth buffer section equals to (m×Dm+Pm) memory address for buffering the mth data of the N+1 input data, where m is a nonnegative integer from 0, 1 to N, Dm is the delay of the mth data, and Pm is a nature number representing a predetermined number of memory address for extra buffering the mth data; assigning an empty memory address in the mth buffer section to buffer the mth data; accessing the mth data from where the mth data buffered after buffering the (N+1) data, and outputting the (N+1) data in a (m×Dm) delay sequence. The present invention allocates the memory address effectively, so applying the present invention economizes the use of the memory request.
摘要翻译：用于对（N + 1）个输入数据进行交织并分配相应的存储器的方法和装置包括以下步骤：分配第m个缓冲器部分等于（mxDm + Pm）个存储器地址， N + 1个输入数据的第N个/第N个数据，其中m是从0,1到N的非负整数，Dm是第m个数据的延迟，Pm是自然数表示用于额外缓冲第m个数据的预定数量的存储器地址; 在第m个缓冲区中分配空的存储器地址以缓冲第m个数据; 在缓冲（N + 1）数据之后，访问从第m个数据缓冲的第m个数据，并将（N + 1）数据输出到（m×Dm）延迟序列。本发明有效地分配存储器地址，因此应用本发明节省了存储器请求的使用。

66. 发明申请

US20050268200A1 Method, apparatus, and system for enhancing robustness of predictive video codecs using a side-channel based on distributed source coding techniques 有权
标题翻译：使用基于分布式源编码技术的侧信道来增强预测视频编解码器的鲁棒性的方法，装置和系统
公开(公告)号：US20050268200A1
公开(公告)日：2005-12-01
申请号：US11140086
申请日：2005-05-27
申请人： Harinath Garudadri , Naveen Srinivasamurthy , Hyukjune Chung , Kannan Ramachandran , Abhik Majumdar
发明人： Harinath Garudadri , Naveen Srinivasamurthy , Hyukjune Chung , Kannan Ramachandran , Abhik Majumdar
IPC分类号： H04N19/89 , G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , H04L1/22
CPC分类号： H04L1/0014 , H04L1/22 , H04L2001/0096 , H04N19/39 , H04N19/395
摘要： A method, apparatus, and system for providing distributed source coding techniques that improve data coding performance, such as video data coding, when channel errors or losses occur. Errors in the reconstruction of the data is eliminated or reduced by sending extra information. Correlation between a predicted sequence and an original sequence can be used to design codebooks and find the cosets required to represent the original image. This information may be sent over another channel, or a secondary channel.
摘要翻译：一种用于提供分布式源编码技术的方法，装置和系统，其在信道错误或丢失发生时提供诸如视频数据编码的数据编码性能。通过发送额外的信息消除或减少数据重建中的错误。可以使用预测序列和原始序列之间的相关性来设计码本并找到表示原始图像所需的陪集。该信息可以通过另一个信道或辅助信道发送。

67. 发明申请

US20050268199A1 Method and circuit for reducing SATA transmission data errors by adjusting the period of sending ALIGN primitives 有权
标题翻译：通过调整发送ALIGN原语的周期来减少SATA传输数据错误的方法和电路
公开(公告)号：US20050268199A1
公开(公告)日：2005-12-01
申请号：US11039923
申请日：2005-01-24
申请人： Pao-Ching Tseng , Shu-Fang Tsai , Chuan Liu
发明人： Pao-Ching Tseng , Shu-Fang Tsai , Chuan Liu
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04J3/07 , H04L1/00 , H04L12/28 , H04L12/56
CPC分类号： H04L1/0001 , H04L25/49
摘要： A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.
摘要翻译：通过调整发送两个连续的ALIGN原语的周期来减少SATA（串行高级技术附件）传输数据错误的方法和电路。该方法以预定周期读取8b / 10b编码错误计数器的计数值，并根据计数值调整发送两个连续的ALIGN原语的周期。由于系统根据通道条件动态调整发送两个连续ALIGN原语的周期，因此可以减少SATA传输数据的错误。

68. 发明申请

US20050257114A1 Cyclic redundancy check circuit for use with self-synchronous scramblers 有权
公开(公告)号：US20050257114A1
公开(公告)日：2005-11-17
申请号：US11167122
申请日：2005-06-28
申请人： Steven Gorshe
发明人： Steven Gorshe
IPC分类号： H03M13/09 , H04L1/00 , G06F11/00 , G06F11/10 , G06F11/30 , G08C25/00 , H03M13/00
CPC分类号： H03M13/09
摘要： The present invention provides a circuit for detecting and correcting errors in a bit stream. The circuit consists of a plurality of circuit elements, a least one operation circuit means, and at least two logic gates. The logic gates receive inputs from the plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. The operation circuit elements perform bitwise operations on the contents of at least two of the circuit elements. The bitwise operations are dictated by a cyclical redundancy check (CRC) polynomial and are used to perform the CRC error detection division operation. At the end of the division process for the data to be checked, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.

69. 发明申请

US20050229070A1 Method of detecting error location, and error detection circuit, error correction circuit, and reproducing apparatus using the method 失效
标题翻译：检测误差位置的方法，误差检测电路，误差校正电路和使用该方法的再现装置
公开(公告)号：US20050229070A1
公开(公告)日：2005-10-13
申请号：US11092894
申请日：2005-03-30
申请人： Miyuki Okamoto , Satoshi Kanai , Masato Fuma
发明人： Miyuki Okamoto , Satoshi Kanai , Masato Fuma
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , G11B20/18 , G11C29/00 , H03M13/00 , H03M13/03 , H03M13/37 , H04L1/00
CPC分类号： H04L1/0071 , G11B20/18 , G11B2020/1272 , H04L1/0045 , H04L1/0061
摘要： An error correction circuit capable of detecting burst errors included in a data signal with reliability. The error correction circuit comprises a reading unit, a first estimation unit, a second estimation unit, and a correction unit. The reading unit reads the data signal. The first estimation unit estimates error locations based on BIS code included in the data signal, and stores the locations into an error location storing unit. The second estimation unit estimates error locations based on characteristics of bit strings adjoining the BIS code, and stores the locations into the error location storing unit. The correction unit identifies erasure locations based on the error locations stored in the error location storing unit, and performs erasure correction on the erasure locations identified. Since the error locations are estimated based on the BIS code and the characteristics of the bit strings adjoining the BIS code as well, it is possible to detect burst errors without fail.
摘要翻译：一种能够可靠地检测包括在数据信号中的突发错误的纠错电路。误差校正电路包括读取单元，第一估计单元，第二估计单元和校正单元。读取单元读取数据信号。第一估计单元基于包括在数据信号中的BIS码来估计误差位置，并将位置存储到错误位置存储单元中。第二估计单元基于与BIS码相邻的位串的特性来估计误差位置，并将位置存储到错误位置存储单元中。校正单元基于存储在错误位置存储单元中的错误位置识别擦除位置，并且对所识别的擦除位置执行擦除校正。由于错误位置也是基于BIS代码和与BIS码相邻的位串的特性来估计的，所以可以毫不费力地检测突发错误。

70. 发明申请

US20050207483A1 Discrete multi-tone (DMT) system and method that communicates a data pump data stream between a general purpose CPU and a DSP via a buffering scheme 有权
公开(公告)号：US20050207483A1
公开(公告)日：2005-09-22
申请号：US11093520
申请日：2005-03-30
申请人： Charles Polk
发明人： Charles Polk
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04B1/38 , H04L1/00 , H04L27/26
CPC分类号： H04L1/0071 , H04L1/0045 , H04L1/08 , H04L27/2626 , H04L2001/0094
摘要： The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式