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71. 发明授权

US07876847B2 Global minimum-based MLD demapping for soft-output MIMO detection 有权
标题翻译：用于软输出MIMO检测的全局最小化MLD解映射
公开(公告)号：US07876847B2
公开(公告)日：2011-01-25
申请号：US11085026
申请日：2005-03-16
申请人： Nils Graef , Joachim S. Hammerschmidt
发明人： Nils Graef , Joachim S. Hammerschmidt
IPC分类号： H04L23/02
CPC分类号： H04L1/06 , H04L5/023
摘要： A method for generating soft bit values for a multi-bit symbol encoded in one or more received signals comprises (a) for a plurality of different combinations of multiple bit values, iteratively generating, for each combination, a metric value based on the one or more received signals. The method further comprises (b) for each iteration, maintaining (i) a global extremum register containing a global extremum of the metric values; (ii) a bit occupancy for the global extremum register; and (iii) a plurality of bit bk registers, one for each bit bk in the symbol. Each bit bk register contains an extremum of the metric values corresponding to combinations of multiple bit values whose bit bk value is opposite the bit bk value of the bit occupancy for the global extremum register. The method further comprises (c) generating, for each bit bk in the symbol, a soft bit value based on a difference between the value in the global extremum register and the value in the corresponding bit bk register.
摘要翻译：一种用于为在一个或多个接收信号中编码的多比特符号产生软比特值的方法包括（a）针对多个比特值的多个不同组合，对于每个组合迭代地生成基于该一个或多个更多的信号。该方法还包括（b）对于每次迭代，维持（i）包含度量值的全局极值的全局极值寄存器; （ii）全球极值登记册的位占有率; 和（iii）多个位bk寄存器，一个用于符号中的每个位bk。每个位bk寄存器包含与位bk值与全局极值寄存器的位占用的位bk值相反的多个位值的组合对应的度量值的极值。所述方法还包括（c）基于所述全局极值寄存器中的值与对应的位bk寄存器中的值之间的差，为符号中的每个位bk产生软比特值。

72. 发明授权

US07873336B2 Frequency offset compensation for communication systems 有权
标题翻译：通讯系统频偏补偿
公开(公告)号：US07873336B2
公开(公告)日：2011-01-18
申请号：US11713178
申请日：2007-03-02
申请人： Fan Fei , Ming-Ju Ho , Dukhyun Kim , Marcel Johannes Gerhardus Vriikorte
发明人： Fan Fei , Ming-Ju Ho , Dukhyun Kim , Marcel Johannes Gerhardus Vriikorte
IPC分类号： H04B1/00 , H04B15/00 , H04B17/00 , H04B1/18 , H04B1/10
CPC分类号： H04L27/2657 , H04L27/2646 , H04L2027/002 , H04L2027/0022
摘要： In communications between a pair of stations using modulated carrier signals, a first station estimates the carrier frequency offset with respect to the second station and transmits signals that are responsive to the estimated carrier frequency offset. The first station may adjust the carrier frequency of the signals it transmits in response to the estimated carrier frequency offset, and/or transmit data to the second station representing the estimated carrier frequency offset. The second station adjusts the carrier frequency of the signals it transmits to the first station, and/or compensates for carrier frequency offset in its processing of received signals, in response to estimated carrier frequency offset data received from the first station.
摘要翻译：在使用调制载波信号的一对站之间的通信中，第一站估计相对于第二站的载波频率偏移，并发送响应于所估计的载波频率偏移的信号。第一站可以响应于估计的载波频率偏移来调整其发送的信号的载波频率，和/或将数据发送到表示估计的载波频率偏移的第二站。响应于从第一站接收到的估计的载波频率偏移数据，第二站调整其发送到第一站的信号的载波频率和/或在接收信号的处理中补偿载波频率偏移。

73. 发明授权

US07861036B2 Double degraded array protection in an integrated network attached storage device 有权
标题翻译：集成网络连接存储设备中双重降级阵列保护
公开(公告)号：US07861036B2
公开(公告)日：2010-12-28
申请号：US11857024
申请日：2007-09-18
申请人： Richard J. Byrne , Eu Gene Goh , Zhi Ping He , Nevin C. Heintze , Yun Peng , Silvester Tjandra , Xing Zhao
发明人： Richard J. Byrne , Eu Gene Goh , Zhi Ping He , Nevin C. Heintze , Yun Peng , Silvester Tjandra , Xing Zhao
IPC分类号： G06F12/00
CPC分类号： G06F12/1458 , G06F11/1092 , G06F2211/1016 , G06F2211/103 , G06F2211/1059
摘要： In one embodiment, the invention provides a method for accessing a physical storage-device array comprising a plurality of storage devices. The method includes (1) obtaining at least one parameter from a profile selected from two or more profiles concurrently defining two or more virtual arrays, each profile defining (i) a different virtual array associated with a corresponding set of storage devices and (ii) a parameter set of one or more parameters used for accessing the virtual array; and (2) generating an instruction, based on the at least one parameter, for accessing, or disallowing access to, information in the virtual array defined by the selected profile, wherein a parameter in each the parameter set defined by each profile indicates whether two or more storage devices in the corresponding virtual array are degraded.
摘要翻译：在一个实施例中，本发明提供一种用于访问包括多个存储设备的物理存储设备阵列的方法。该方法包括：（1）从两个或多个配置文件中选择的配置文件中选择的至少一个参数，同时定义两个或多个虚拟阵列，每个配置文件定义（i）与对应的一组存储设备相关联的不同虚拟阵列，以及（ii）用于访问虚拟阵列的一个或多个参数的参数集; 以及（2）基于所述至少一个参数生成用于访问或不允许对由所选择的简档定义的虚拟阵列中的信息的访问的指令，其中由每个简档定义的每个参数集中的参数指示是否两个或相应的虚拟阵列中的更多的存储设备劣化。

74. 发明授权

US07860174B2 Method and apparatus for frequency domain compensation of DC offset in an orthogonal frequency division multiplexing system 有权
标题翻译：正交频分复用系统中DC偏移频域补偿的方法和装置
公开(公告)号：US07860174B2
公开(公告)日：2010-12-28
申请号：US11141271
申请日：2005-05-31
申请人： Joachim S. Hammerschmidt , Xiaowen Wang
发明人： Joachim S. Hammerschmidt , Xiaowen Wang
IPC分类号： H04K1/10
CPC分类号： H04L27/2647 , H04L25/06
摘要： Methods and systems are provided for estimating the DC offset distortion in a receiver. A fast Fourier transform is applied to at least a portion of a preamble portion of the received signal; an impact of the DC offset distortion on one or more empty subcarriers is determined; individual DC estimates are derived based on each of the determinations; and each of the individual DC estimates are combined to obtain an overall DC estimate.
摘要翻译：提供了用于估计接收机中的DC偏移失真的方法和系统。快速傅里叶变换被应用于接收信号的前导码部分的至少一部分; 确定DC偏移失真对一个或多个空子载波的影响; 基于每个测定得出个体直流估计值; 并且将每个单独的DC估计值组合以获得总体DC估计。

75. 发明授权

US07852133B2 Phase-locked loop (PLL) having extended tracking range 有权
标题翻译：锁相环（PLL）具有扩展的跟踪范围
公开(公告)号：US07852133B2
公开(公告)日：2010-12-14
申请号：US12159246
申请日：2007-09-28
申请人： Yhean-Sen Lai , Jie Song , Zhenyu Wang , Jinguo Yu
发明人： Yhean-Sen Lai , Jie Song , Zhenyu Wang , Jinguo Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0991 , H04L2027/0046
摘要： A method for extending a tracking range of a PLL includes the steps of: establishing an initial tracking window of the PLL, the tracking window having a first width associated therewith; and dynamically adjusting the tracking window of the PLL within an extended tracking range when a frequency of an input signal supplied to the PLL is outside of the tracking window, the extended tracking range having a second width associated therewith which is greater than the first width.
摘要翻译：用于扩展PLL的跟踪范围的方法包括以下步骤：建立PLL的初始跟踪窗口，跟踪窗口具有与之相关联的第一宽度; 以及当提供给所述PLL的输入信号的频率在所述跟踪窗口之外时，在扩展跟踪范围内动态调整所述PLL的跟踪窗口，所述扩展跟踪范围具有大于所述第一宽度的第二宽度。

76. 发明授权

US07848473B2 Phase interpolator having a phase jump 有权
标题翻译：相位内插器具有相位跳变
公开(公告)号：US07848473B2
公开(公告)日：2010-12-07
申请号：US11020021
申请日：2004-12-22
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H04L7/04
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0337
摘要： A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal. In addition, according to the present invention, the roaming tap interpolator includes a delay unit that selectively delays one or more of the first signal and the second signal to generate an interpolation signal, the interpolation signal selectively having a first phase or a second phase.
摘要翻译：公开了一种基于漫游抽头内插器来产生相位控制数据的方法和装置。本发明认识到，漫游抽头内插器在每个内插区域的边界处具有固有的非线性和不连续性。公开了一种漫游抽头内插器，其在时间上偏移插值曲线，以避免插值曲线中的不需要的伪影。漫游抽头内插器通常包括多个延迟元件，其延迟第一信号以产生每个具有相关联的相位的多个内插区域; 多路复用器，用于选择一个或多个插值区域; 以及内插器，用于处理所选择的一个或多个内插区域以产生第二信号。此外，根据本发明，漫游抽头内插器包括延迟单元，其选择性地延迟第一信号和第二信号中的一个或多个以产生内插信号，该内插信号选择性地具有第一相位或第二相位。

77. 发明授权

US07847666B2 Differential inductor for use in integrated circuits 有权
标题翻译：差分电感用于集成电路
公开(公告)号：US07847666B2
公开(公告)日：2010-12-07
申请号：US11535501
申请日：2006-09-27
申请人： Shahriar Moinian , John E. Scoggins
发明人： Shahriar Moinian , John E. Scoggins
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F2017/0046 , H01F2017/008 , H01F2021/125 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor device in an integrated circuit includes a first winding portion, a bridge portion and a second winding portion. The integrated circuit has a first, a second, a third and a fourth metallization level. The first winding portion comprises a first metal line formed on the first metallization level and a second metal line formed on the second metallization level, the first metal line being electrically connected in parallel with the second metal line. The bridge portion comprises a third metal line formed on the third metallization level and a fourth metal line formed on the fourth metallization level, the third metal line being electrically connected in parallel with the fourth metal line. The second winding portion comprises a fifth metal line formed on the first metallization level and a sixth metal line formed on the second metallization level, the fifth metal line being electrically connected in parallel with the sixth metal line. The bridge portion electrically connects the first winding portion to the second winding portion.
摘要翻译：集成电路中的电感器件包括第一绕组部分，桥接部分和第二绕组部分。集成电路具有第一，第二，第三和第四金属化层。第一绕组部分包括形成在第一金属化层上的第一金属线和形成在第二金属化层上的第二金属线，第一金属线与第二金属线并联电连接。桥接部分包括形成在第三金属化层上的第三金属线和形成在第四金属化层上的第四金属线，第三金属线与第四金属线并联电连接。第二绕组部分包括形成在第一金属化层上的第五金属线和形成在第二金属化层上的第六金属线，第五金属线与第六金属线并联电连接。桥接部分将第一绕组部分电连接到第二绕组部分。

78. 发明授权

US07840756B2 RAID storage system with tandem operation using multiple virtual profiles 有权
标题翻译： RAID存储系统使用多个虚拟配置文件进行串联操作
公开(公告)号：US07840756B2
公开(公告)日：2010-11-23
申请号：US11982262
申请日：2007-10-31
申请人： Richard Joseph Byrne
发明人： Richard Joseph Byrne
IPC分类号： G06F12/16
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0617 , G06F3/0632 , G06F3/065 , G06F3/0689 , G06F2211/1045
摘要： An improved RAID storage system adapted to selectively and automatically store the same data “in tandem” using two different storage profiles. In one embodiment, a first store operation occurs in accordance with first storage profile and, if a flag in the first storage profile is set, a second store operation automatically occurs in accordance with a second storage profile but with the same data as stored in the first store operation. The first and second storage profiles are stored sequentially in profile registers within a controller in the storage system. To speed the tandem operation, the data may be held in a re-readable FIFO buffer in the controller. The buffer is sized to hold the minimum size of data that can be stored to the physical disks in the storage system. Preferably, the size of the buffer is substantially equal to the minimum size.
摘要翻译：一种改进的RAID存储系统，其适于使用两种不同的存储配置文件“串联”选择性地和自动地存储相同的数据。在一个实施例中，根据第一存储简档发生第一存储操作，并且如果设置了第一存储配置文件中的标志，则根据第二存储配置文件自动发生第二存储操作，但是存储与第第一店铺经营。第一和第二存储简档被顺序存储在存储系统中的控制器内的简档寄存器中。为了加速串联操作，数据可以保存在控制器中的可读FIFO缓冲器中。缓冲区的大小可以保存可存储到存储系统中的物理磁盘的最小数据量。优选地，缓冲器的尺寸基本上等于最小尺寸。

79. 发明申请

US20100293388A1 PROTECTING SECRET INFORMATION IN A PROGRAMMED ELECTRONIC DEVICE 有权
标题翻译：保护编程电子设备中的秘密信息
公开(公告)号：US20100293388A1
公开(公告)日：2010-11-18
申请号：US12444160
申请日：2006-10-06
申请人： Gerhard Ammer , Michael Chambers , Hai Wang , Paul Renshaw , Michael Kiessling
发明人： Gerhard Ammer , Michael Chambers , Hai Wang , Paul Renshaw , Michael Kiessling
IPC分类号： G06F11/30 , G06F21/24
CPC分类号： G06F21/78 , G06F21/575
摘要： This disclosure provides a way for securely protecting secret information—for example, a secret key—in a programmed electronic device. A technique is disclosed for protecting secret information in a programmed electronic device that includes a non-trusted memory containing software, a data memory containing the secret information, and an access restriction logic unit that is adapted to allow or block access to the secret information wherein the secret information is adapted to be used for verifying the integrity of the software. In one embodiment, when starting up the programmed electronic device, the access restriction logic unit allows access to the secret information. Then the secret information is accessed for use in verifying the integrity of the software, and subsequently the access restriction logic unit blocks further access to the secret information. Embodiments of a semiconductor device and a programmed electronic device comprising similar features are also disclosed.
摘要翻译：本公开提供了一种用于安全地保护秘密信息的方式，例如编程电子设备中的秘密密钥。公开了一种用于保护编程的电子设备中的秘密信息的技术，其包括含有软件的不可信存储器，包含秘密信息的数据存储器，以及适于允许或阻止访问秘密信息的访问限制逻辑单元，其中，秘密信息适用于验证软件的完整性。在一个实施例中，当启动编程电子设备时，访问限制逻辑单元允许访问秘密信息。然后访问秘密信息以用于验证软件的完整性，随后访问限制逻辑单元阻止对秘密信息的进一步访问。还公开了包括相似特征的半导体器件和编程电子器件的实施例。

80. 发明授权

US07830857B2 Credit-based wireless network scheduling 有权
标题翻译：基于信用的无线网络调度
公开(公告)号：US07830857B2
公开(公告)日：2010-11-09
申请号：US11427476
申请日：2006-06-29
申请人： Jinhui Li
发明人： Jinhui Li
IPC分类号： H04J3/24
CPC分类号： H04L47/10 , H04L47/14 , H04L47/30 , H04L47/39 , H04W28/12 , H04W28/26 , H04W72/12
摘要： A scheduler having improved fairness is disclosed, for scheduling packets or other data blocks for transmission from a plurality of transmission elements in timeslots in a communication system. The scheduler determines credit measures for respective ones of the transmission elements, with each of said credit measures being a function of a reserved portion of an available bandwidth and a scheduled portion of said available bandwidth for a corresponding one of the transmission elements. The scheduler selects one or more of the transmission elements for scheduling in a given one of the timeslots based on the credit measures. The scheduler in an illustrative embodiment may be implemented in a network processor integrated circuit or other processing device of the communication system.
摘要翻译：公开了一种具有改进的公平性的调度器，用于在通信系统中的时隙中调度分组或其他数据块以从多个传输元件发送。调度器为相应的传输单元确定信用度量，其中每个信用度量是可用带宽的保留部分和所述可用带宽的调度部分的函数，用于相应的一个传输单元。调度器基于信用度量来选择在给定的时隙中的一个或多个用于调度的传输元素。说明性实施例中的调度器可以在通信系统的网络处理器集成电路或其他处理设备中实现。

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