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71. 发明授权

US09023706B2 Transistor and method for forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US09023706B2
公开(公告)日：2015-05-05
申请号：US14023426
申请日：2013-09-10
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/66 , H01L29/78 , H01L21/265 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/26513 , H01L21/2654 , H01L21/26546 , H01L21/823807 , H01L21/823814 , H01L29/517 , H01L29/518 , H01L29/7848
摘要： The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.
摘要翻译：晶体管及其形成方法技术领域本发明涉及晶体管及其形成方法。本发明的晶体管包括半导体衬底; 形成在所述半导体衬底上的栅介电层; 形成在栅介质层上的栅极; 栅介电层下的沟道区; 以及位于所述半导体衬底中以及在所述沟道区的相应侧上的源极区和漏极区，其中所述源极和漏极区中的至少一个包括与所述沟道区相邻并且沿垂直方向布置的一组位错到半导体衬底的顶表面，并且该位错集包括至少两个位错。

72. 发明授权

US09013918B2 Two-terminal memory cell and semiconductor memory device based on different states of stable current 有权
标题翻译：基于不同稳态电流的双端存储单元和半导体存储器件
公开(公告)号：US09013918B2
公开(公告)日：2015-04-21
申请号：US13320331
申请日：2011-08-10
申请人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/39 , G11C17/06 , H01L27/102
CPC分类号： G11C11/39 , G11C17/06 , G11C2213/72 , G11C2213/74 , H01L27/1027
摘要： A two-terminal memory cell includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the memory cell by applying a reverse bias, which is approaching to the reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the memory cell may be effectively used for data storage.
摘要翻译：双端存储单元包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来将第一数据状态存储在存储单元中。可以通过在第一P型半导体层和第二N型半导体层之间施加接近存储单元的反向击穿区域的反向偏压来将第二数据状态存储在存储单元中。以这种方式，存储单元可以有效地用于数据存储。

73. 发明授权

US08969930B2 Gate stack structure, semiconductor device and method for manufacturing the same 有权
标题翻译：栅叠层结构，半导体器件及其制造方法
公开(公告)号：US08969930B2
公开(公告)日：2015-03-03
申请号：US13321886
申请日：2011-04-06
申请人： Haizhoou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhoou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/28 , H01L29/66
CPC分类号： H01L21/28247 , H01L29/66545 , H01L29/78
摘要： A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part of the gate in thickness, the thickness of the removed part of the gate on the active region is greater than the thickness of the removed part of the gate on the connection region so as to expose opposite inner walls of the sidewall spacer; forming an isolation dielectric layer on the gate to cover the exposed inner walls. There is also provided a semiconductor device and a method for manufacturing the same. The methods can reduce the possibility of short-circuit occurring between the gate and the second contact hole and can be compatible with the dual-contact-hole process.
摘要翻译：栅极堆叠结构包括形成在栅极上并嵌入栅极中的隔离电介质层。侧壁间隔物覆盖隔离电介质层的相对侧面，并且位于有源区上的隔离电介质层比位于连接区上的隔离电介质层厚。一种用于制造栅极堆叠结构的方法包括去除栅极的一部分厚度，有源区上的栅极的去除部分的厚度大于连接区域上的栅极的去除部分的厚度，以便露出侧壁间隔件的相对的内壁; 在栅极上形成隔离电介质层以覆盖暴露的内壁。还提供了一种半导体器件及其制造方法。该方法可以降低栅极和第二接触孔之间发生短路的可能性，并且可以与双接触孔工艺兼容。

74. 发明授权

US08969164B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08969164B2
公开(公告)日：2015-03-03
申请号：US14002456
申请日：2012-03-23
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/08 , H01L21/84 , H01L27/12 , H01L21/8234 , H01L29/51
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/51 , H01L29/66431
摘要： A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.
摘要翻译：半导体结构包括衬底，栅极堆叠，基极区域和源极/漏极区域，其中栅极堆叠层位于基极区域上，源极/漏极区域位于基极区域中，并且基极区域是位于基板上。在基部区域和基板之间设置支撑隔离结构，其中支撑结构的一部分连接到基板; 在基部区域和基板之间设置空腔，其中空腔由基底区域，基底和支撑隔离结构构成。在栅极堆叠的两侧，基部区域和支撑隔离结构上设置应力材料层。相应地，提供了一种用于制造这种半导体结构的方法，其抑制短沟道效应，降低寄生电容和漏电流，并且增强源/漏区的陡度。

75. 发明授权

US08946071B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08946071B2
公开(公告)日：2015-02-03
申请号：US14364950
申请日：2012-03-23
申请人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
发明人： Jun Luo , Chao Zhao , Huicai Zhong , Junfeng Li , Dapeng Chen
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/84 , H01L29/417 , H01L29/45
CPC分类号： H01L21/823814 , H01L21/2255 , H01L21/28518 , H01L21/823418 , H01L21/823443 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/41725 , H01L29/45 , H01L29/456 , H01L29/665
摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved.
摘要翻译：本发明公开了一种半导体器件的制造方法，包括：在基板上形成栅叠层结构; 在栅极层叠结构的两侧形成源极/漏极区域和栅极侧壁间隔物; 至少在源/漏区中沉积镍基金属层; 进行第一退火，使得源极/漏极区中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使富Ni相的金属硅化物转变为镍系金属硅化物，同时在镍基金属硅化物与源极/漏极区之间的界面处形成掺杂离子的偏析区域。根据本发明的方法在将掺杂离子注入到金属硅化物的富Ni相中之后执行退火，从而提高掺杂离子的固溶度并形成高度浓缩的掺杂离子的偏析区，因此SBH 镍基金属二氧化硅和源极/漏极区域之间的金属 - 半导体接触被有效地降低，接触电阻降低，并且器件的驱动能力得到改善。

76. 发明授权

US08932927B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08932927B2
公开(公告)日：2015-01-13
申请号：US13816065
申请日：2011-12-01
申请人： Huajie Zhou , Qiuxia Xu
发明人： Huajie Zhou , Qiuxia Xu
IPC分类号： H01L21/00 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66477 , H01L29/66795 , H01L29/785
摘要： The present application discloses a semiconductor device structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising a local SOI structure having a local buried isolation dielectric layer; forming a fin on the silicon substrate on top of the local buried isolation dielectric layer; forming a gate stack structure on the top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof is simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated, therefore, short channel effects are suppressed desirably, and MOSFETs are boosted to develop towards a trend of downscaling size.
摘要翻译：本申请公开了一种半导体器件结构及其制造方法，其中所述方法包括：形成包括具有局部掩埋隔离电介质层的局部SOI结构的半导体衬底; 在硅衬底上在本地掩埋隔离介质层的顶部形成翅片; 在翅片的顶面和侧面形成栅极堆叠结构; 在栅极堆叠结构的两侧形成鳍片中的源极/漏极结构; 并执行金属化。本发明利用传统的基于平面的基于自顶向下的方法，其制造过程简单易行; 本发明表现出与CMOS平面工艺的良好兼容性并且可以容易地集成，因此期望短抑制沟道效应，并且MOSFET被增强以朝向缩小尺寸的趋势发展。

77. 发明授权

US08878615B2 Voltage-controlled oscillator device and method of correcting voltage-controlled oscillator 有权
标题翻译：压控振荡器装置及校正压控振荡器的方法
公开(公告)号：US08878615B2
公开(公告)日：2014-11-04
申请号：US13518958
申请日：2011-10-09
申请人： Yuping Wu , Lan Chen
发明人： Yuping Wu , Lan Chen
IPC分类号： H03B1/04 , H03L1/00 , H03L7/099 , H03L7/00
CPC分类号： H03L7/00 , H03L7/099
摘要： The present application discloses a voltage-controlled oscillator device and a method of correcting the voltage-controlled oscillator. The voltage-controlled oscillator device comprises predistortion module, configured to predistort an input voltage to obtain a predistorted voltage; and a voltage-controlled oscillator, configured to generate an output signal with a corresponding oscillation frequency according to the predistorted voltage, wherein the predistortion module corrects a non-linear characteristic of the voltage-controlled oscillator, so that there is a linear relationship between the input voltage and the oscillation frequency of the output signal. The voltage-controlled oscillator device may be applied to a phase-locked circuit in a communication system.
摘要翻译：本申请公开了一种压控振荡器装置和校正压控振荡器的方法。压控振荡器装置包括：预失真模块，被配置为预失真输入电压以获得预失真电压; 以及电压控制振荡器，被配置为根据所述预失真电压产生具有相应振荡频率的输出信号，其中所述预失真模块校正所述压控振荡器的非线性特性，使得所述压控振荡器之间存在线性关系输入电压和输出信号的振荡频率。压控振荡器装置可以应用于通信系统中的锁相电路。

78. 发明授权

US08828881B2 Etch-back method for planarization at the position-near-interface of an interlayer dielectric 有权
标题翻译：在层间电介质的位置 - 接近界面处用于平坦化的蚀刻反向法
公开(公告)号：US08828881B2
公开(公告)日：2014-09-09
申请号：US13381005
申请日：2011-08-10
申请人： Lingkkuan Meng , Huaxiang Yin
发明人： Lingkkuan Meng , Huaxiang Yin
IPC分类号： H01L21/3065 , H01L21/3105 , H01L21/768 , H01L29/78
CPC分类号： H01L21/31055 , H01L21/76801 , H01L29/78
摘要： The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.
摘要翻译：本发明公开了一种用于在层间电介质（ILD）的位置 - 接近界面处的平坦化的回蚀刻方法，包括：通过化学气相沉积或氧化方法在晶片的表面上沉积或生长厚SiO 2层; 旋涂一层SOG，然后进行热处理以获得相对均匀的堆叠结构; 使用等离子体蚀刻对SOG进行回蚀，并且在接近SiO 2的位置 - 接近界面时停止; 在靠近界面的位置处对剩余的SOG / SiO 2结构进行等离子体回蚀，直到达到期望的厚度。由于在位置 - 接近界面处进行两步蚀刻，因此获得了非常好的ILD平滑表面。也就是说，ILD的平面和整洁的表面不仅在中心区域中获得，而且在晶片的边缘处获得。

79. 发明申请

US20140231923A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20140231923A1
公开(公告)日：2014-08-21
申请号：US14346537
申请日：2012-05-16
申请人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/76232 , H01L21/823807 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7846 , H01L29/7848
摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.
摘要翻译：本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。相应地，本发明还提供一种制造半导体结构的方法。在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加通道电流，从而有效地提高了半导体结构的性能。

80. 发明授权

US08802518B2 Semiconducor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08802518B2
公开(公告)日：2014-08-12
申请号：US13395608
申请日：2011-10-17
申请人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L21/8234 , H01L29/51 , H01L29/423
CPC分类号： H01L21/82345 , H01L21/28114 , H01L21/823468 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.
摘要翻译：一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

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