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    • 71. 发明授权
    • Offset-reduced hall sensor
    • 偏移式霍尔传感器
    • US07119538B2
    • 2006-10-10
    • US10810323
    • 2004-03-26
    • Lothar Blossfeld
    • Lothar Blossfeld
    • G01R33/07H01L43/06
    • G01D5/147G01D5/145
    • A technique for determining an offset-reduced Hall voltage (Uh), and/or an offset voltage (UH, offset) of a Hall sensor (1) includes applying a Hall sensor current (I) at first and second taps (a1, a2, a3) of the Hall sensor (1), and determining a first Hall voltage (Uh1) at third and fourth taps (a3, a4) displaced from the first and second taps (a1, a2, a5). A second Hall sensor current is applied modified relative to the first, and a second Hall voltage (Uh2) is determined. The Hall voltage (Uh) and/or Hall voltage offset (Uh,offset) are determined from the first and second Hall voltages. To compensate any offset present, a second measurement applies the second Hall sensor current I at taps (a3, a4) that are spatially displaced relative to the first and/or second taps.
    • 一种用于确定霍尔传感器(1)的偏移降低的霍尔电压(Uh)和/或偏移电压(UH,偏移)的技术包括在第一和第二抽头(a 1, a 1,a 2,a 3),并且确定在从第一和第二抽头(a 1,a 2,...)移位的第三和第四抽头(a 3,a 4)处的第一霍尔电压(Uh 1) a 5)。 施加相对于第一霍尔传感器电流的第二霍尔传感器电流,并确定第二霍尔电压(Uh 2)。 从第一和第二霍尔电压确定霍尔电压(Uh)和/或霍尔电压偏移(Uh,偏移)。 为了补偿存在的任何偏移,第二测量将第二霍尔传感器电流I应用于相对于第一和/或第二抽头在空间上移位的抽头(a 3,a 4)。
    • 72. 发明授权
    • Method and device for simultaneously representing at least a first and a second sequence of pictures in an overall picture
    • 用于同时表示总体图像中的至少第一和第二图像序列的方法和装置
    • US07106384B1
    • 2006-09-12
    • US09913103
    • 2000-02-01
    • Günter Scheffler
    • Günter Scheffler
    • H04N5/45
    • H04N5/45
    • The invention relates to a method and a device for simultaneously representing at least a first and a second sequence of pictures (M, S) in an overall picture. The inventive method is characterised in that picture data belonging to a picture of the first sequence of pictures (M) is stored in the form of a first picture data signal in a first picture memory (SPM). Picture data belonging to a picture of the second sequence of pictures (S) is stored in the form of a second picture data signal in a second picture memory (SPS). The picture data of the first and second picture data memory is read out according to a periodic screen signal (RS), whereby phase shift (SHIFTM, SHIFTS, tx) of the screen signal (RS) can be adjusted according to the first and/or second picture data signal.
    • 本发明涉及一种用于同时表示总体图像中的至少第一和第二图像序列(M,S)的方法和装置。 本发明的方法的特征在于,属于第一图像序列(M)的图像的图像数据以第一图像数据信号的形式存储在第一图像存储器(SP M M)中。 属于第二图像序列(S)的图像的图像数据以第二图像数据信号的形式存储在第二图像存储器(SP S S S)中。 根据周期性屏幕信号(RS)读出第一和第二图像数据存储器的图像数据,由此相位移动(SHIFT MIT,SHIFT,S < 可以根据第一和/或第二图像数据信号来调整屏幕信号(RS)的“SUB> x”)。
    • 74. 发明授权
    • Method and production of a sensor
    • 传感器的方法和生产
    • US06964927B2
    • 2005-11-15
    • US10149560
    • 2001-12-07
    • Günter IgelMarkus Rogalla
    • Günter IgelMarkus Rogalla
    • H01L21/56H01L31/0203H01L31/0232H01L21/302
    • H01L31/0203H01L21/565H01L2924/0002H01L2924/00
    • The invention relates to a method for producing a sensor (1), wherein a carrier chip (2) is produced. Said chip is provided with a sensor structure (3) comprising an active sensor surface (4). A material (9) capable of flowing is applied onto carrier chips (2) in such a way that the sensor structure (3) has a thinner layer thickness on said active sensor surface (4) than on the area of the carrier chip (2) which borders on the active sensor surface (4). The material (9) which is capable of flowing is hardened thereafter. The hardened material (9) is subsequently removed by chemical means from the surface which faces said carrier chip (2) until the active sensor surface of the sensor structure is layed bare.
    • 本发明涉及一种制造传感器(1)的方法,其中制造了载体芯片(2)。 所述芯片设置有包括有源传感器表面(4)的传感器结构(3)。 将能够流动的材料(9)施加到载体芯片(2)上,使得传感器结构(3)在所述主动传感器表面(4)上具有比载体芯片(2)的区域更薄的层厚度 ),其接合在主动传感器表面(4)上。 能够流动的材料(9)之后被硬化。 随后通过化学方法从面向所述载体芯片(2)的表面去除硬化材料(9),直到传感器结构的有源传感器表面裸露。
    • 76. 发明授权
    • Apparatus using bus capacitance to perform data storage during data transfer across the bus
    • 使用总线电容在总线数据传输期间执行数据存储的装置
    • US06928506B2
    • 2005-08-09
    • US09747279
    • 2000-12-21
    • Martin CzechMichael Albert
    • Martin CzechMichael Albert
    • G06F13/40G06F13/14G11C11/24
    • G06F13/4077
    • The invention relates to a circuit arrangement with two or more circuit sections, which cooperate through a data transfer device. The invention solves the problem of double area expenditure for two memory devices for each receiver, in that the data bus itself takes over the role of one of these memory devices, namely that of the memory device functioning as master. For this it is only necessary to integrate a single memory device on the data bus, which takes over the role of the no longer needed memory device for each data receiver. By saving the memory device associated with each receiver, the semiconductor chip area needed for communication buses can be optimized and the master memory device of the prior art may be replaced by the bus capacitance.
    • 本发明涉及具有两个或多个电路部分的电路装置,其通过数据传送装置进行协作。 本发明解决了每个接收机的两个存储器件的双面积支出的问题,因为数据总线本身承担了这些存储器件之一的作用,即作为主器件的存储器件的作用。 为此,仅需要在数据总线上集成单个存储器件,其接管每个数据接收器不再需要的存储器件的作用。 通过保存与每个接收器相关联的存储器件,可以优化通信总线所需的半导体芯片面积,并且现有技术的主存储器件可以被总线电容代替。