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71. 发明授权

US10559691B2 Compact OTP/MTP memory device including a cavity formed between a substrate and a buried oxide layer 有权
公开(公告)号：US10559691B2
公开(公告)日：2020-02-11
申请号：US16195150
申请日：2018-11-19
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Kiok Boone Quek
IPC分类号： H01L29/78 , H01L27/112 , H01L23/525 , H01L29/66 , H01L21/84 , H01L27/12
摘要： Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.

72. 发明授权

US10510859B2 Reduced capacitance coupling effects in devices 有权
公开(公告)号：US10510859B2
公开(公告)日：2019-12-17
申请号：US16393028
申请日：2019-04-24
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shyue Seng Tan , Kiok Boone Elgin Quek , Eng Huat Toh
IPC分类号： H01L23/535 , H01L29/49 , H01L29/51 , H01L29/78 , H01L23/522 , H01L29/66 , H01L21/28 , H01L21/02
摘要： A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

73. 发明申请

US20190043992A1 INTEGRATED CIRCUITS WITH MEMORY CELLS AND METHODS FOR PRODUCING THE SAME 审中-公开
公开(公告)号：US20190043992A1
公开(公告)日：2019-02-07
申请号：US15665888
申请日：2017-08-01
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Yuan Sun , Shyue Seng Tan
IPC分类号： H01L29/788 , H01L29/423 , H01L29/45 , H01L29/08 , H01L23/535 , H01L21/285 , H01L21/768 , H01L29/66
CPC分类号： H01L29/7881 , H01L21/28518 , H01L21/76895 , H01L23/535 , H01L29/0847 , H01L29/40114 , H01L29/42328 , H01L29/45 , H01L29/66825
摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a source, a drain, and a channel defined between the source and drain. A memory cell overlies the channel, where the memory cell includes a floating gate and a control gate overlying the floating gate. A block overlies a portion of the drain referred to as a blocked drain region, where the blocked drain region is adjacent to the channel. A drain silicide overlies the drain and terminates at the blocked drain region such that the blocked drain region is between the drain silicide and the channel.

74. 发明授权

US09905642B2 Corner transistor suppression 有权
公开(公告)号：US09905642B2
公开(公告)日：2018-02-27
申请号：US15138339
申请日：2016-04-26
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shyue Seng Tan , Ying Keung Leung , Elgin Quek
IPC分类号： H01L21/70 , H01L21/336 , H01L21/76 , H01L29/06 , H01L21/8234 , H01L21/762 , H01L27/088
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/088
摘要： The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.

75. 发明授权

US09728721B2 Resistive memory device 有权
公开(公告)号：US09728721B2
公开(公告)日：2017-08-08
申请号：US14340582
申请日：2014-07-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shyue Seng Tan , Eng Huat Toh , Xuan Anh Tran , Yuan Sun , Elgin Kiok Boone Quek
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/16 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/144 , H01L45/146
摘要： A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors.

76. 发明授权

US09178138B2 Method for forming a PCRAM with low reset current 有权
标题翻译：低复位电流形成PCRAM的方法
公开(公告)号：US09178138B2
公开(公告)日：2015-11-03
申请号：US14324703
申请日：2014-07-07
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shyue Seng Tan , Eng Huat Toh
IPC分类号： H01L29/78 , H01L45/00 , H01L21/8239
CPC分类号： H01L45/06 , H01L45/122 , H01L45/1226 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.
摘要翻译：相变存储器结构由超薄加热器衬垫和超薄相变层形成，从而增加加热容量并降低复位电流。实施例包括在底部电极上形成第一层间电介质（ILD），去除第一ILD的一部分，形成电池区域，在电池区域内形成u形加热器衬垫，在U形形状内形成层间电介质结构所述层间电介质结构包括在所述第一ILD的顶表面上方延伸的突出部分，在所述突出部分的侧表面和/或围绕所述突出部分的所述第一ILD上形成相变层，以及形成电介质围绕突出部分的间隔物。

77. 发明授权

US09087988B1 Compact localized RRAM cell structure realized by spacer technology 有权
公开(公告)号：US09087988B1
公开(公告)日：2015-07-21
申请号：US14633508
申请日：2015-02-27
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2445 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1675 , H01L45/1691
摘要： An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.

78. 发明授权

US09064951B2 Deep depleted channel MOSFET with minimized dopant fluctuation and diffusion levels 有权
标题翻译：深度耗尽的沟道MOSFET，掺杂剂波动和扩散水平最小
公开(公告)号：US09064951B2
公开(公告)日：2015-06-23
申请号：US14177983
申请日：2014-02-11
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Eng Huat Toh , Shyue Seng Tan
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L29/165
CPC分类号： H01L29/78 , H01L29/1045 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6659 , H01L29/66651 , H01L29/7834
摘要： CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity.
摘要翻译： CMOS器件由具有最小化掺杂剂波动和扩散的沟道层制造。实施例包括在一对衬垫之间在衬底上形成一个虚拟栅极，在衬底中形成由接地平面层分隔开的源极和漏极，从衬底去除虚拟栅极，在该对间隔物之间形成空腔在去除所述虚拟栅极之后，在所述衬底上形成沟道层，在所述沟道层和所述腔的侧表面上形成高k层，并且在所述空腔中形成替换栅极。

79. 发明申请

US20140342542A1 STRUCTURE AND METOHDS OF IMPROVING RELIABILITY OF NON-VOLATILE MEMORY DEVICES 有权
标题翻译：提高非易失性存储器件可靠性的结构和性能
公开(公告)号：US20140342542A1
公开(公告)日：2014-11-20
申请号：US14448691
申请日：2014-07-31
申请人： GLOBALFOUNDRIES Singapore PTE LTD
发明人： Shyue Seng Tan
IPC分类号： H01L29/423 , H01L29/49 , H01L29/66 , H01L29/51
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234 , H01L29/4916 , H01L29/512 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A method includes forming a patterned gate stack for a memory device, the patterned gate stack including a gate insulation layer, a charge storage layer, a blocking insulation layer and a gate electrode, the gate insulation layer and the blocking insulation layer having an initial width. An etching process is performed on the patterned gate stack to selectively remove at least a portion of each of the gate insulation layer and the blocking insulation layer, the etching process reducing a width of each of the gate insulation layer and the blocking insulation layer from the initial width to a final width. After performing the etching process, at least one material layer is formed proximate sidewalls of the patterned gate stack, the at least one material layer laterally confining each of the gate insulation layer, the charge storage layer, the blocking insulation layer, and the gate electrode.
摘要翻译：一种方法包括形成用于存储器件的图案化栅极堆叠，所述图案化栅极堆叠包括栅极绝缘层，电荷存储层，阻挡绝缘层和栅极电极，所述栅极绝缘层和阻挡绝缘层具有初始宽度。在图案化的栅极堆叠上进行蚀刻处理以选择性地去除栅极绝缘层和阻挡绝缘层中的每一个的至少一部分，蚀刻工艺将栅极绝缘层和阻挡绝缘层中的每一个的宽度从初始宽度到最终宽度。在执行蚀刻工艺之后，在图案化的栅叠层的侧壁附近形成至少一个材料层，至少一个材料层横向限制栅极绝缘层，电荷存储层，阻挡绝缘层和栅电极。

80. 发明授权

US08772108B1 Multi-time programmable non-volatile memory 有权
标题翻译：多时间可编程非易失性存储器
公开(公告)号：US08772108B1
公开(公告)日：2014-07-08
申请号：US13775844
申请日：2013-02-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Eng Huat Toh , Shyue Seng Tan , Elgin Quek
IPC分类号： H01L29/66
CPC分类号： H01L29/7881 , H01L27/11558 , H01L29/42328 , H01L29/66825
摘要： A process for creating a low-cost multi-time programmable (MTP) non-volatile memory (NVM) and the resulting device are provided. Embodiments include forming a select gate and a floating gate above a substrate, each over a first shallow trench isolation (STI) region, a doped region formed between a source and a drain, and a second STI region, forming a metal layer over the floating gate, and forming a pair of self-aligned contacts on the first and second STI regions on opposite sides of the doped region, respectively, and electrically connected to the metal layer.
摘要翻译：提供了一种用于创建低成本多时间可编程（MTP）非易失性存储器（NVM）和所得到的装置的过程。实施例包括在衬底上形成选择栅极和浮置栅极，每个在第一浅沟槽隔离（STI）区域上形成，在源极和漏极之间形成的掺杂区域和第二STI区域，在浮置区域上形成金属层并且分别在掺杂区域的相对侧上的第一和第二STI区域上形成一对自对准触点，并且电连接到金属层。

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