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71. 发明授权

US07525833B2 Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers 有权
标题翻译：使用微米/纳米级移位寄存器的纳米级移位寄存器和信号解复用
公开(公告)号：US07525833B2
公开(公告)日：2009-04-28
申请号：US11255722
申请日：2005-10-21
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0023 , G11C19/00 , G11C2213/17 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches, each series controlled by common latch-control signals. Internal latches of each series of latches are alternatively interconnected with a previous latch of the other series and a next latch of the other series by two series of gates, each controlled by a gate signal line.
摘要翻译：本发明的一个实施例是纳米级移位寄存器，其可以在某些纳米尺度和混合尺度的逻辑电路中用于将输入信号分配到逻辑电路的各个纳米线。在所描述的实施例中，纳米尺度移位寄存器包括两个系列的纳米尺度锁存器，每个串联由公共锁存控制信号控制。每个锁存器系列的内部锁存器交替地与另一个串联的先前锁存器和另一个串联的下一个锁存器通过两个串联的栅极互连，每个栅极由栅极信号线控制。

72. 发明授权

US07517794B2 Method for fabricating nanoscale features 有权
标题翻译：制造纳米尺度特征的方法
公开(公告)号：US07517794B2
公开(公告)日：2009-04-14
申请号：US11256513
申请日：2005-10-21
申请人： Gregory S. Snider , Phillip J. Kuekes
发明人： Gregory S. Snider , Phillip J. Kuekes
IPC分类号： H01L21/4763
CPC分类号： H01L27/0805 , H01L21/743 , H01L21/76885
摘要： One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then etched, and a conductive material is deposited into the troughs to form nanowires and into the trough segments to form nanowire segments. The exposed surfaces of nanowires are coated with a protective coating, and the conductive material of the nanowire segments is then removed to produce trough segments etched through the nanoimprinting resist and the silicon layer. A dielectric column between configurably resistive columns in orientations non-parallel with the orientation of the nanowires is fabricated above the nanowires, gate signal lines are fabricated above, and parallel with, the dielectric column, and latch-control signal lines are fabricated above, and parallel with, the configurably resistive columns. Additional embodiments of the present invention are directed to fabricating devices and circuits with nanoscale features by partitioning the nanoscale features into sets, and separately coating the features of each set prior to one or more subsequent steps.
摘要翻译：本发明的一个实施例是一种制造纳米级移位寄存器的方法。在所描述的实施例中，施加在绝缘体上硅衬底上的纳米压印抗蚀剂层被纳米压印以形成槽和槽段。然后在槽和槽段的底部暴露的硅层被蚀刻，并且将导电材料沉积到槽中以形成纳米线并进入槽段以形成纳米线段。纳米线的暴露表面涂覆有保护涂层，然后去除纳米线段的导电材料，以产生通过纳米压印抗蚀剂和硅层蚀刻的槽段。在纳米线上面制造与纳米线的取向不平行取向的可配置电阻柱之间的电介质柱，栅极信号线在电介质柱上方并与其并联，并且上面制造锁存控制信号线，并且与可配置的电阻柱平行。本发明的另外的实施例涉及制造具有纳米尺度特征的器件和电路，通过将纳米尺度特征分成几组，并且在一个或多个后续步骤之前分别涂覆每个组的特征。

73. 发明申请

US20080238478A1 FPGA architecture at conventonal and submicron scales 有权
标题翻译： FPGA架构在conventonal和亚微米尺度
公开(公告)号：US20080238478A1
公开(公告)日：2008-10-02
申请号：US12156877
申请日：2008-06-04
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , B82Y10/00 , B82Y30/00 , G11C8/10 , G11C13/0007 , G11C13/0014 , G11C2213/15 , G11C2213/34 , G11C2213/51 , G11C2213/77 , G11C2213/81 , H03K19/17728 , H03K19/1778
摘要： Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.
摘要翻译：公开了可重构逻辑器件和编程器件的方法。逻辑器件包括查找表（LUT）和配置用于对LUT输出信号进行采样的至少一个存储元件。 LUT包括多个输入信号，可操作地耦合到输入信号的可编程阻抗装置的阵列和LUT输出信号。阵列中的每个可编程阻抗器件包括可操作地耦合到输入信号中的一个的第一电极，设置成形成其中第二电极至少部分地与第一电极重叠的结的第二电极和设置在第一电极和第二电极。可编程材料可操作地耦合第一电极和第二电极，使得每个可编程阻抗装置呈现非易失性可编程阻抗。该阵列可以被配置为一维或二维阵列。

74. 外观设计

USD571676S1 Light line generating device 有权
标题翻译：光线发生装置
公开(公告)号：USD571676S1
公开(公告)日：2008-06-24
申请号：US29299278
申请日：2007-12-21
申请人： Gregory S. Snider
设计人： Gregory S. Snider

75. 发明授权

US07358614B2 Antisymmetric nanowire crossbars 有权
标题翻译：反对称纳米线交叉杆
公开(公告)号：US07358614B2
公开(公告)日：2008-04-15
申请号：US11079763
申请日：2005-03-08
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G11C13/0002 , B82Y10/00 , G11C2213/77 , G11C2213/81 , H04Q3/0004 , Y10S977/762
摘要： Various embodiments of the present invention are directed to antisymmetric nanowire-crossbar-circuit designs. Antisymmetric nanowire crossbars are composed, in certain embodiments of the present invention, of two or more microregions that receive input signals and two or more microregions that send output signals. Antisymmetric nanowire crossbars may include a nanowire-crossbar network having signal paths that carry signals between one or more of the microregions. The nanowire-crossbar network may also carry signals between external electronic devices and one or more of the microregions. Antisymmetric nanowire crossbars may additionally include two or more structures that supply voltage and ground.
摘要翻译：本发明的各种实施例涉及反对称纳米线 - 横向电路设计。在本发明的某些实施例中，反对称纳米线交叉杆由接收输入信号的两个或多个微区域和发送输出信号的两个或更多微区域组成。反对称纳米线交叉杆可以包括具有在一个或多个微区域之间携带信号的信号路径的纳米线交叉网络。纳米线交叉网络还可以在外部电子设备与一个或多个微区域之间携带信号。反对称纳米线交叉杆可以另外包括两个或更多个提供电压和接地的结构。

76. 发明授权

US07257016B2 Enhanced nanowire-crossbar latch array 有权
标题翻译：增强型纳米线交叉闭锁阵列
公开(公告)号：US07257016B2
公开(公告)日：2007-08-14
申请号：US11136950
申请日：2005-05-24
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G11C11/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/54 , G11C2213/77 , G11C2213/81 , Y10S977/762
摘要： Various embodiments of the present invention are directed to a signal-storing nanowire-crossbar latch array. In one embodiment, the signal-storing nanowire-crossbar latch array is fabricated from three signal lines, including an enable line and two control lines, that cross and intersect with a number of signal wires. Signals are stored in the nanowire-crossbar latch array, and output from the nanowire-crossbar latch array, by applying an input signal to each signal wire and applying selected voltages and voltage pulses to the control lines. In alternate embodiments, a second enable line that crosses and interconnects with each signal wire is added to the nanowire-crossbar latch array.
摘要翻译：本发明的各种实施例涉及一种信号存储纳米线交叉闭锁阵列。在一个实施例中，信号存储纳米线交叉开关锁存阵列由三个信号线制成，包括使能线和两个控制线，其与多个信号线交叉并相交。信号通过将输入信号施加到每个信号线并将选定的电压和电压脉冲施加到控制线，将信号存储在纳米线交叉开关锁存阵列中，并从纳米线交叉开关锁存阵列输出。在替代实施例中，与每个信号线交叉并与其互连的第二使能线被添加到纳米线交叉开关锁存阵列。

77. 发明授权

US07254799B2 Method for allocating resources in heterogeneous nanowire crossbars having defective nanowire junctions 失效
标题翻译：用于在具有缺陷纳米线结的异质纳米线交叉杆中分配资源的方法
公开(公告)号：US07254799B2
公开(公告)日：2007-08-07
申请号：US11047981
申请日：2005-01-31
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G06F17/50
CPC分类号： G11C13/02 , B82Y10/00 , G11C29/025 , G11C2213/77 , G11C2213/81 , H01L27/10 , Y10S977/932 , Y10S977/94
摘要： Various embodiments of the present invention provide methods for allocating nanowire junctions in a nanowire crossbar having one or more randomly distributed non-functional crossbar nanowire junctions. In certain embodiments, the method constructs a circuit graph based on the circuit and constructs a crossbar graph based on the nanowire crossbar. A search is then conducted, in the embodiments, in order to determine a monomorphism that respectively maps the nodes and edges of the circuit graph to a subset of nodes and a subset of edges of the crossbar graph. The subset of nodes and subset of edges of the crossbar graph can then be used to allocate nanowire junctions in the nanowire crossbar.
摘要翻译：本发明的各种实施方案提供了在具有一个或多个随机分布的非功能横梁纳米线结的纳米线横截面中分配纳米线结的方法。在某些实施例中，该方法基于该电路构建电路图，并且基于该纳米线交叉开关构建交叉图。然后在实施例中进行搜索，以便确定将电路图的节点和边缘分别映射到节点的子集和交叉图的边缘的子集的单态。节点的子集和交叉图的边缘子集可以用于在纳米线横截面中分配纳米线结。

78. 发明授权

US07227379B1 Nanoscale latch-array processing engines 有权
标题翻译：纳米级闩锁阵列处理引擎
公开(公告)号：US07227379B1
公开(公告)日：2007-06-05
申请号：US11192197
申请日：2005-07-27
申请人： Gregory S. Snider , Philip J. Kuekes , Duncan R. Stewart
发明人： Gregory S. Snider , Philip J. Kuekes , Duncan R. Stewart
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： B82Y10/00 , G06N99/007 , H01L27/101
摘要： One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions. Nanoscale-latch arrays can be combined and interconnected in an almost limitless number of different ways to construct arbitrarily complex, sequential, parallel, or both parallel and sequential computing engines that represent additional embodiments of the present invention.
摘要翻译：本发明的一个实施例是通过纳米线总线互连以形成锁存阵列的纳米级锁存器的阵列。纳米尺度锁存阵列中的每个纳米级锁存器用作纳米尺度寄存器，并由纳米尺度控制线驱动。锁存阵列的原始操作可以被定义为一个或多个输入到纳米线数据总线和纳米尺度控制线中的一个或多个的序列。在本发明的各种锁存阵列实施例中，可以以受控的方式将信息从一个纳米级锁存器传送到另一个纳米级锁存器，并且可以设计信息传输操作的序列以实现任意的布尔逻辑运算，并且运算符包括NOT， AND，OR，XOR，NOR，NAND和其他这样的布尔逻辑运算符和操作，以及输入和输出功能。纳秒级锁存器阵列可以以几乎无限数量的不同方式组合和互连，以构造代表本发明附加实施例的任意复杂，顺序，并行或并行和顺序的计算引擎。

79. 发明授权

US07159195B2 Reduction of storage elements in synthesized synchronous circuits 失效
标题翻译：减少合成同步电路中的存储元件
公开(公告)号：US07159195B2
公开(公告)日：2007-01-02
申请号：US10683030
申请日：2003-10-10
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for reducing a number of storage elements in a synthesized synchronous circuit. In one embodiment, the circuit is represented as a directed, partitioned graph. The graph is divided into a plurality of time-ordered timeslots that are bounded by storage elements. The strongly-connected components (SCCs) in the graph are first identified. For each middle SCC where there is slack between the middle SCC and a first SCC and slack between the middle SCC and a second SCC, a time-slot-relative direction is selected for moving the middle SCC. The direction is selected as a function of a number of storage elements required for moving the middle SCC toward the first SCC versus moving the middle SCC toward the second SCC. The middle SCC is then moved in the selected time-slot-relative direction.
摘要翻译：用于减少合成同步电路中的多个存储元件的方法和装置。在一个实施例中，电路被表示为有向的分区图。该图被划分为由存储元件限定的多个时间有序的时隙。首先确定图中强连接的组件（SCC）。对于中间SCC与第一SCC之间松弛的中间SCC和中间SCC与第二SCC之间的松弛，选择时隙相对方向来移动中间SCC。根据将中间SCC朝向第一SCC移动所需的存储元件的数量的方式被选择，而不是将中间SCC朝向第二SCC移动。然后中间的SCC在选定的时隙相对方向移动。

80. 外观设计

USD516401S1 Self-centering door lock guide 失效
标题翻译：自定心门锁导轨
公开(公告)号：USD516401S1
公开(公告)日：2006-03-07
申请号：US29195358
申请日：2003-12-10
申请人： Gregory S. Snider , James E. Pangerc
设计人： Gregory S. Snider , James E. Pangerc

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