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71. 发明授权

US09406506B2 Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon 有权
标题翻译：晶格匹配的纵横比捕获，以减少在硅上直接生长的III-V层的缺陷
公开(公告)号：US09406506B2
公开(公告)日：2016-08-02
申请号：US14534131
申请日：2014-11-05
申请人： International Business Machines Corporation
发明人： Keith E. Fogel , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/02 , H01L29/20 , H01L29/06
CPC分类号： H01L21/02587 , H01L21/02381 , H01L21/02387 , H01L21/0243 , H01L21/02461 , H01L21/02463 , H01L21/02488 , H01L21/02538 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/02658 , H01L21/3086 , H01L21/7605 , H01L21/76224 , H01L21/8252 , H01L29/0657 , H01L29/20 , H01L29/66431
摘要： A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.
摘要翻译：应用于电子器件的结构包括在晶格失配衬底上具有高晶体质量和低缺陷密度的III-V层。沟槽形成在具有不同晶格常数的衬底上生长的III-V族半导体材料层中。电介质材料沉积在沟槽内，形成电介质区域。去除III-V材料层的一部分，留下由电介质区域限定的新的沟槽。在初始沉积的III-V半导体层的剩余部分和由电介质区域限定的沟槽内生长具有降低的缺陷密度的新的III-V半导体材料层。

72. 发明授权

US09401372B1 Dual isolation on SSOI wafer 有权
公开(公告)号：US09401372B1
公开(公告)日：2016-07-26
申请号：US14618442
申请日：2015-02-10
申请人： International Business Machines Corporation
发明人： Bruce B. Doris , Hong He , Ali Khakifirooz , Junli Wang
IPC分类号： H01L21/00 , H01L27/12 , H01L21/84 , H01L21/762 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/027 , H01L21/3105 , H01L27/092 , H01L21/8238 , H01L29/06 , H01L29/66
CPC分类号： H01L27/1207 , H01L21/02532 , H01L21/3086 , H01L21/76283 , H01L21/8238 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66795
摘要： A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

73. 发明申请

US20160204194A1 METHOD AND STRUCTURE FOR IMPROVING FINFET WITH EPITAXY SOURCE/DRAIN 有权
标题翻译：用于改进外部源/排水的FINFET的方法和结构
公开(公告)号：US20160204194A1
公开(公告)日：2016-07-14
申请号：US15074587
申请日：2016-03-18
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Tenko Yamashita
IPC分类号： H01L29/06 , H01L29/66 , H01L29/417 , H01L29/78
CPC分类号： H01L29/0653 , H01L21/32139 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/41791 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/6681 , H01L29/7848 , H01L29/785
摘要： Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of the isolation structures. Sidewalls of the gate material bock define ends of gate structures to be subsequently formed. The isolation structures obstruct lateral growth of a semiconductor material during a selective epitaxial grown process in formation of source/drain regions, thereby preventing merging of the source/drain regions at the ends of gate structures. As a result, a lateral distance between each sidewall of the gate material block and a corresponding outermost sidewall of an array of a plurality of semiconductor fins can be made sufficiently small without causing the electrical shorts of the source/drain regions.
摘要翻译：隔离结构形成为横向围绕栅极材料块，使得栅极材料块的每个侧壁邻接隔离结构的相应侧壁。栅极材料块的侧壁限定随后形成的栅极结构的端部。隔离结构在形成源极/漏极区域期间的选择性外延生长工艺期间阻挡半导体材料的横向生长，从而防止栅极结构端部处的源极/漏极区域的合并。结果，可以使栅极材料块的每个侧壁与多个半导体鳍片的阵列的对应的最外侧壁之间的横向距离足够小，而不会引起源极/漏极区域的电短路。

74. 发明申请

US20160197189A1 METHOD TO CONTROLLABLY ETCH SILICON RECESS FOR ULTRA SHALLOW JUNCTIONS 有权
公开(公告)号：US20160197189A1
公开(公告)日：2016-07-07
申请号：US15070584
申请日：2016-03-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/78 , H01L29/08 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/18 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.

75. 发明申请

US20160190247A1 STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR 审中-公开
公开(公告)号：US20160190247A1
公开(公告)日：2016-06-30
申请号：US15064143
申请日：2016-03-08
申请人： International Business Machines Corporation
发明人： Martin M. Frank , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/06 , H01L29/78 , H01L21/311 , H01L29/49 , H01L21/84 , H01L21/3213 , H01L29/66 , H01L29/423
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/31105 , H01L21/31111 , H01L21/32133 , H01L21/84 , H01L27/1203 , H01L29/401 , H01L29/41783 , H01L29/4232 , H01L29/42356 , H01L29/42364 , H01L29/4238 , H01L29/42392 , H01L29/49 , H01L29/66545 , H01L29/775 , H01L29/7842 , H01L29/78696
摘要： A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.

76. 发明申请

US20160187288A1 NANOFLUID SENSOR WITH REAL-TIME SPATIAL SENSING 有权
标题翻译：具有实时空间感知功能的南非传感器
公开(公告)号：US20160187288A1
公开(公告)日：2016-06-30
申请号：US14587941
申请日：2014-12-31
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： G01N27/414 , H01L21/84 , H01L27/12
CPC分类号： G01N27/4145 , G01N27/4146 , G01N27/4148 , H01L21/84 , H01L27/1203
摘要： A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.
摘要翻译：提供了能够在纳米流体内实现纳米颗粒的实时空间感测的半导体结构。该结构包括栅极结构的阵列。层间电介质材料围绕栅结构阵列。垂直入口通道位于层间电介质材料的一部分内，并位于栅极结构阵列的一侧。垂直出口通道位于层间电介质材料的另一部分内，并位于栅结构阵列的另一侧。用作后门的水平通道与垂直入口和出口通道流体连通，位于门结构阵列下方。背栅介质材料部分在垂直入口通道，垂直出口通道和水平通道内排列暴露表面。

77. 发明申请

US20160181352A1 CAPACITOR STRUCTURE COMPATIBLE WITH NANOWIRE CMOS 审中-公开
标题翻译：电容器结构与纳米CMOS兼容
公开(公告)号：US20160181352A1
公开(公告)日：2016-06-23
申请号：US14581043
申请日：2014-12-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L49/02 , H01L27/06
CPC分类号： H01L28/60 , B81B1/00 , H01L27/0629 , H01L29/0669 , H01L29/0673 , H01L29/413
摘要： A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
摘要翻译：提供一种半导体器件，其包括存在于半导体材料的至少一层上的绝缘材料的基座以及与绝缘材料的基座接触的至少一个翅片结构。源区和漏区结构存在于至少一个鳍结构的相对侧上。源极和漏极区域结构中的至少一个包括至少两个外延材料层。第一外延材料层与至少一层半导体材料接触。第二外延材料层与至少一个翅片结构接触。第一外延材料层通过第二外延材料层与至少一个翅片结构分离。存在于至少一个翅片结构上的栅极结构。

78. 发明申请

US20160172460A1 FINFET SPACER WITHOUT SUBSTRATE GOUGING OR SPACER FOOT 有权
标题翻译：不带衬底的FINFET隔板或间隔脚
公开(公告)号：US20160172460A1
公开(公告)日：2016-06-16
申请号：US14568287
申请日：2014-12-12
申请人： International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Ali Khakifirooz , Raghavasimhan Sreenivasan
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/823431
摘要： The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming a spacer adjacent to a gate in a fin field effect transistor (FinFET) device without resulting in substrate gouging or a spacer foot. A conformal spacer layer may be formed around a plurality of fins and a gate, wherein the conformal spacer layer may have a thickness above the plurality of fins that is at least one-half the distance between the individual fins. An isotropic etch may be used to remove excess spacer material around the plurality of fins (but not between the fins) and around the gate. An anisotropic etch may be used to remove the remaining spacer material from between the fins and around the gate, leaving a spacer adjacent to the gate without gouging the substrate surface between the fins.
摘要翻译：本发明一般涉及半导体器件，更具体地说，涉及在鳍状场效应晶体管（FinFET）器件中形成与栅极相邻的隔离物而不产生衬底气刨或间隔脚的结构和方法。可以在多个翅片和栅极周围形成共形间隔层，其中保形间隔层可以具有在多个翅片之上的厚度，其为单个翅片之间的距离的至少一半。可以使用各向同性蚀刻来去除多个翅片周围的多余的隔离材料（而不是在翅片之间）和栅极周围。可以使用各向异性蚀刻从散热片和栅极之间移除剩余的间隔物材料，留下与栅极相邻的间隔物，而不在翅片之间刨削基板表面。

79. 发明申请

US20160163808A1 SEMICONDUCTOR DEVICE WITH LOW-K GATE CAP AND SELF-ALIGNED CONTACT 审中-公开
公开(公告)号：US20160163808A1
公开(公告)日：2016-06-09
申请号：US15009288
申请日：2016-01-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Charan V. V. S. Surisetty
IPC分类号： H01L29/423 , H01L23/535 , H01L29/78
CPC分类号： H01L29/4232 , H01L21/76814 , H01L21/7682 , H01L21/76829 , H01L21/76831 , H01L21/76897 , H01L23/535 , H01L29/66545 , H01L29/6659 , H01L29/78 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption.

80. 发明授权

US09362182B2 Forming strained fins of different material on a substrate 有权
标题翻译：在基材上形成不同材料的应变片
公开(公告)号：US09362182B2
公开(公告)日：2016-06-07
申请号：US14534678
申请日：2014-11-06
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Bruce B. Doris , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/336 , H01L21/84 , H01L21/8234 , H01L27/12 , H01L27/092
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/785
摘要： A method, and the resulting structure, of forming two fins with different types of strain and material on the same substrate.
摘要翻译：在同一基板上形成具有不同类型的应变和材料的两个翅片的方法和所得到的结构。

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