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71. 发明申请

US20150221767A1 SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES 有权
标题翻译：垂直场效应晶体管，具有共享源/漏区的每个对象的半导体结构和形成结构的方法
公开(公告)号：US20150221767A1
公开(公告)日：2015-08-06
申请号：US14169318
申请日：2014-01-31
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66666 , H01L21/3086 , H01L21/823425 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/42392 , H01L29/66484 , H01L29/7827 , H01L29/7831
摘要： Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical FETs. Specifically, a U-shaped semiconductor body has a horizontal section and two vertical sections. The horizontal section comprises a shared source/drain region for first and second vertical FETs. Each vertical section comprises a channel region and a source/drain region above the channel region for a corresponding one the vertical FETs. In one semiconductor structure, each vertical section has a gate wrapped around the channel region. In another semiconductor structure, each vertical section has a front gate positioned adjacent to the inner vertical surface at the channel region and a back gate positioned adjacent to the outer vertical surface at the channel region. In any case, a contact, which is electrically isolated from the gates, extends vertically to the shared source/drain region in the horizontal section. Optionally, metal strap(s) electrically connect the pair of vertical FETs to adjacent pair(s).
摘要翻译：公开了形成结构的半导体结构和方法。这些结构各自包括一对垂直FET。具体地说，U形半导体本体具有水平截面和两个垂直截面。水平部分包括用于第一和第二垂直FET的共享源极/漏极区域。每个垂直部分包括沟道区域和沟道区域上方的源极/漏极区域，用于相应的一个垂直FET。在一个半导体结构中，每个垂直部分具有缠绕在沟道区域周围的栅极。在另一个半导体结构中，每个垂直部分具有位于相邻于通道区域处的内部垂直表面的前门和位于沟道区域处与外部垂直表面相邻的后门。在任何情况下，与栅极电隔离的触点在水平部分中垂直延伸到共享的源极/漏极区域。可选地，金属带将一对垂直FET电连接到相邻对。

72. 发明授权

US09041107B2 Devices with gate-to-gate isolation structures and methods of manufacture 有权
标题翻译：具有栅极到栅极隔离结构的器件和制造方法
公开(公告)号：US09041107B2
公开(公告)日：2015-05-26
申请号：US13833735
申请日：2013-03-15
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/12 , H01L29/06 , H01L21/02 , H01L21/762 , H01L21/84
CPC分类号： H01L29/0649 , H01L21/02038 , H01L21/76283 , H01L21/845
摘要： Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.
摘要翻译：提供具有栅极到栅极隔离结构和制造方法的器件。该方法包括在衬垫膜和下面的衬底中形成多个隔离结构。该方法还包括形成包括隔离结构的多个翅片和包括两个垫片膜的第二多个翅片以及下面的衬底的一部分，每个鳍片由沟槽分开。该方法还包括去除第二多个翅片的部分，导致比包括隔离结构的多个翅片的高度低的高度。该方法还包括在每个沟槽内形成栅电极，将第二多个鳍片和包括隔离结构的多个翅片的邻接侧面相互掩埋。包括隔离结构的多个翅片电和物理地隔离栅电极的相邻栅电极。

73. 发明授权

US09040383B2 Devices with gate-to-gate isolation structures and methods of manufacture 有权
公开(公告)号：US09040383B2
公开(公告)日：2015-05-26
申请号：US13772993
申请日：2013-02-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/76 , H01L29/06 , H01L21/02 , H01L21/762 , H01L21/84
CPC分类号： H01L29/0649 , H01L21/02038 , H01L21/76283 , H01L21/845
摘要： Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad films and a portion of the underlying substrate, each of which are separated by a trench. The method further includes removing portions of the second plurality of fins resulting in a height lower than a height of the plurality of fins including the isolation structures. The method further includes forming gate electrodes within each trench, burying the second plurality of fins and abutting sides of the plurality of fins including the isolation structures. The plurality of fins including the isolation structures electrically and physically isolate adjacent gate electrode of the gate electrodes.

74. 发明申请

US20140332888A1 SEMICONDUCTOR DEVICE INCLUDING FINFET STRUCTURES WITH VARIED EPITAXIAL REGIONS, RELATED METHOD AND DESIGN STRUCTURE 有权
标题翻译：包括具有各种外延区域的FINFET结构的半导体器件，相关方法和设计结构
公开(公告)号：US20140332888A1
公开(公告)日：2014-11-13
申请号：US13889848
申请日：2013-05-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/66795
摘要： A semiconductor device including a substrate; a FINFET disposed on the substrate, the FINFET including: a set of epitaxial regions disposed in a source/drain region on a set of fins, the set of epitaxial regions including: a first epitaxial region on a first inner surface of a first outer fin, the first epitaxial region having a first thickness defined as one of: a distance from the first inner surface to an edge of the epitaxial region in the case of a non-merged state of adjacent inner epitaxial regions of adjacent fins, and half of a distance from the first inner surface to an opposing inner surface of an adjacent fin in a merged state of adjacent inner epitaxial regions of adjacent fins, and a second epitaxial region with a second thickness disposed on a first outer surface of the first outer fin. The second thickness is thinner than the first thickness.
摘要翻译：一种包括衬底的半导体器件; 设置在所述衬底上的FINFET，所述FINFET包括：设置在一组鳍片上的源极/漏极区域中的一组外延区域，所述一组外延区域包括：在第一外部鳍片的第一内表面上的第一外延区域所述第一外延区域具有第一厚度，所述第一厚度被定义为在相邻鳍片的相邻内部外延区域的非合并状态的情况下从所述第一内表面到所述外延区域的边缘的距离，在相邻散热片的相邻内部外延区域的合并状态下从相邻散热片的第一内表面到相对的内表面的距离，以及设置在第一外翅片的第一外表面上的具有第二厚度的第二外延区域。第二厚度比第一厚度薄。

75. 发明授权

US08765516B2 Low cost solar cell manufacture method employing a reusable substrate 失效
标题翻译：低成本太阳能电池制造方法采用可重复使用的基板
公开(公告)号：US08765516B2
公开(公告)日：2014-07-01
申请号：US13761371
申请日：2013-02-07
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/00
CPC分类号： H01L31/186 , H01L31/0248 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.
摘要翻译：描述了可重复使用的基板和用于形成单晶硅太阳能电池的方法。形成光伏电池的方法包括在单晶硅衬底上形成中间层，在中间层上形成单晶硅层，并在单晶硅层中形成电特征。该方法还包括在单晶硅层中形成开口，并且通过选择性地通过开口蚀刻中间层，从而将单晶硅层从衬底上分离出来。

76. 发明授权

US08753929B2 Structure fabrication method 有权
标题翻译：结构制造方法
公开(公告)号：US08753929B2
公开(公告)日：2014-06-17
申请号：US13866162
申请日：2013-04-19
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Victor W. C. Chan , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A structure fabrication method. A provided structure includes a gate dielectric region on the substrate and a gate electrode region on the gate dielectric region. Atoms are implanted in a top portion of the gate electrode region, which expands the top portion of the gate electrode in a direction parallel to a top surface of the gate dielectric region. After the atom implantation, a conformal dielectric layer is formed on top and side walls of the gate electrode region. A dielectric spacer layer, formed on the conformal dielectric layer, is etched such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line through that point and parallel to a reference direction intersects the conformal dielectric layer. The reference direction is perpendicular to the top surface of the gate dielectric region.
摘要翻译：一种结构制造方法。所提供的结构包括衬底上的栅极电介质区域和栅极电介质区域上的栅电极区域。原子被注入到栅极电极区域的顶部，该栅极电极区域的顶部在与栅极电介质区域的顶表面平行的方向上扩展栅电极的顶部。在原子注入之后，在栅电极区域的顶壁和侧壁上形成共形绝缘层。蚀刻形成在保形电介质层上的电介质间隔层，使得仅保留在保形绝缘层之下的电介质隔离层的间隔部分，其中对于剩余间隔部分的任何点，通过该点和平行于参考方向与保形电介质层相交。参考方向垂直于栅介质区域的顶表面。

77. 发明申请

US20140110765A1 FIELD EFFECT TRANSISTOR HAVING PHASE TRANSITION MATERIAL INCORPORATED INTO ONE OR MORE COMPONENTS FOR REDUCED LEAKAGE CURRENT 有权
标题翻译：具有相变过渡材料的场效应晶体管合并成一个或多个组件以减少漏电流
公开(公告)号：US20140110765A1
公开(公告)日：2014-04-24
申请号：US13656819
申请日：2012-10-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kota V. R. M. Murali , Edward J. Nowak , Stuart P. Parkin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/28088 , H01L29/4966 , H01L29/4983 , H01L29/66545
摘要： Disclosed is a metal oxide semiconductor field effect transistor (MOSFET) having phase transition material incorporated into one or more components and an associated method. The MOSFET can comprise an asymmetric gate electrode having a phase transition material section (e.g., a chromium or titanium-doped vanadium dioxide (VO2) section) above the drain-side of the channel region. Additionally or alternatively, the MOSFET can comprise source and drain contact landing pads comprising different phase transition materials (e.g., un-doped VO2 and chromium or titanium-doped VO2, respectively). In any case, the phase transition material(s) are pre-selected so as to be insulative when the MOSFET is in the OFF state and the voltage difference between the drain region and the source region (VDS) is high in order to minimize leakage current and so as to be conductive when the MOSFET is in the ON state and VDS is high in order to maintain drive current.
摘要翻译：公开了一种具有并入一个或多个部件中的相变材料的金属氧化物半导体场效应晶体管（MOSFET）和相关方法。 MOSFET可以包括在沟道区域的漏极侧上方具有相变材料部分（例如，铬或钛掺杂的二氧化钒（VO2）部分）的不对称栅极电极。另外或替代地，MOSFET可以包括源极和漏极接触着陆焊盘，其包括不同的相变材料（例如，分别为未掺杂的VO2和铬或钛掺杂的VO2）。在任何情况下，相位迁移材料是预先选择的，以便当MOSFET处于OFF状态并且漏极区域和源极区域（VDS）之间的电压差较高时为绝缘，以便最小化泄漏并且当MOSFET处于导通状态并且VDS为高以便保持驱动电流时导通。

78. 发明申请

US20140077276A1 MIDDLE-OF-LINE BORDERLESS CONTACT STRUCTURE AND METHOD OF FORMING 有权
标题翻译：中间无边界接触结构和形成方法
公开(公告)号：US20140077276A1
公开(公告)日：2014-03-20
申请号：US13623314
申请日：2012-09-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Brent A. Anderson , David V. Horak , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41783 , H01L21/32053 , H01L21/32133 , H01L21/76895 , H01L21/76897 , H01L29/45 , H01L29/6656 , H01L29/78
摘要： Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor.
摘要翻译：所公开的各种实施例包括半导体结构和形成这种结构的方法。在一个实施例中，一种方法包括：提供半导体结构，包括：衬底; 覆盖衬底的至少一个栅极结构; 以及覆盖所述衬底和所述至少一个栅极结构的层间电介质; 去除覆盖衬底的ILD以暴露衬底; 在衬底上形成硅化物层; 在所述硅化物层和所述至少一个栅极结构之上形成导体; 在所述导体中形成开口以暴露所述至少一个栅极结构的栅极区域的一部分; 并在导体的开口中形成电介质。

79. 发明授权

US08643109B2 Isolation region fabrication for replacement gate processing 有权
标题翻译：用于替换门处理的隔离区域制造
公开(公告)号：US08643109B2
公开(公告)日：2014-02-04
申请号：US13771275
申请日：2013-02-20
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/76283 , H01L21/84
摘要： A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
摘要翻译：半导体结构包括绝缘体上硅（SOI）衬底，所述SOI衬底包括底部硅层，掩埋氧化物（BOX）层和顶部硅层; 形成在顶层硅层上的多个有源器件; 以及位于两个有源器件之间的隔离区，其中所述多个有源器件中的至少两个通过所述隔离区域彼此电隔离，并且其中所述隔离区延伸穿过所述顶部硅层到所述BOX层。

80. 发明申请

US20130278281A1 SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS 有权
标题翻译：包括身体连接FET的半导体器件
公开(公告)号：US20130278281A1
公开(公告)日：2013-10-24
申请号：US13922854
申请日：2013-06-20
申请人： International Business Machines Corporation
发明人： Myung-Hee Na , Edward J. Nowak
IPC分类号： G01R31/26
CPC分类号： G01R31/2601 , G01R31/2621
摘要： A semiconductor includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.
摘要翻译：半导体包括：第一场效应晶体管（FET）; 以及与第一FET极性相似的第二FET，其中第一FET的主体电耦合到第二FET的主体，并且第一FET的源极电耦合到第二FET的源极，使得第二FET的体电压控制第一FET的体电压。

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