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    • 71. 发明申请
    • Method of reducing leakage current in sub one volt SOI circuits
    • 降低亚一伏SOI电路漏电流的方法
    • US20050040881A1
    • 2005-02-24
    • US10644211
    • 2003-08-20
    • Richard BrownChing-Te ChuangPeter CookKoushik DasRajiv Joshi
    • Richard BrownChing-Te ChuangPeter CookKoushik DasRajiv Joshi
    • H03K19/00H03K3/01
    • H03K19/0016
    • A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETS) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.
    • 具有降低的亚阈值泄漏的多阈值集成电路(IC)和减少泄漏的方法。 电路逻辑电路和电源连接(Vdd和Ground)之间的可选供电开关器件(NFET和/或PFETS)具有比正常电路器件更高的阈值。 当供电开关装置打开时,一些装置可能具有降低的阈值。 具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。 或者,可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。 中间电源连接在器件上可能具有去耦电容,器件可以锥形化,以获得最佳堆叠高度和最佳锥度比,以最大限度地减少电路泄漏和电路延迟。
    • 75. 发明授权
    • Fireback support apparatus
    • 回火支持设备
    • US4770159A
    • 1988-09-13
    • US120978
    • 1987-11-16
    • Richard BrownJames D. Conner
    • Richard BrownJames D. Conner
    • F24B1/193F24B13/00
    • F24B1/193
    • Fireback support apparatus for supporting a fireback in a fireplace or other area, which does not require attachment to a wall and which provides for varying the angle with respect to the vertical of the fireback. The apparatus includes two base members with flat horizontal surfaces with two vertical upright rear walls, with a transverse opening therebetween and a plurality of steps onto which a fireback is placed for elevational and angular position. Each of the base members also has an opening in the horizontal surface of the upright portion into which legs from a grate may be placed.
    • 用于在壁炉或其他区域中支持反火的回火支撑设备,其不需要附接到墙壁并且提供相对于反火的垂直线的角度的变化。 该装置包括具有平坦水平表面的两个基座构件,其具有两个垂直的竖立后壁,在其间具有横向开口,并且在其上放置用于竖立和倾斜位置的反弹的多个台阶。 每个基座构件还在直立部分的水平表面中具有开口,从炉排可以放置腿部。
    • 76. 发明授权
    • Method for fabricating via connectors through semiconductor wafers
    • 通过半导体晶片制造通孔连接器的方法
    • US4445978A
    • 1984-05-01
    • US473551
    • 1983-03-09
    • James C. WhartenbyRichard BrownSrinivas T. RaoRaymond J. Menna
    • James C. WhartenbyRichard BrownSrinivas T. RaoRaymond J. Menna
    • C25D5/02H01L21/768H05K3/42C25D7/04
    • C25D5/02H01L21/76898H05K3/423
    • A method is provided for fabricating a via connector from a first surface of a semiconductor wafer to an opposite second surface of the wafer. The first step consists of forming an adherent metal layer on the first surface on the semiconductor wafer. If the first surface of the semiconductor wafer has electronic components formed thereon, the metal layer is applied over the electronic components and preferably a protective layer of material is formed over the metal layer. Via holes are then laser drilled at predetermined locations through the metal layer and then through the semiconductor wafer. Thereafter a photoresist layer is applied over the first surface and exposed and developed to provide passage holes in the photoresist which are in alignment with the laser drilled apertures. The metal layer is then connected in the cathode position of the electroforming apparatus and via connectors are thereafter electroformed in the via holes.
    • 提供一种用于从半导体晶片的第一表面到晶片的相对的第二表面制造通孔连接器的方法。 第一步包括在半导体晶片的第一表面上形成粘附金属层。 如果半导体晶片的第一表面具有形成在其上的电子部件,则将金属层施加在电子部件上,并且优选在金属层上形成材料保护层。 然后在预定位置通过金属层激光钻孔,然后穿过半导体晶片。 此后,将光致抗蚀剂层施加在第一表面上并暴露并显影以在光致抗蚀剂中提供与激光钻孔相对准的通孔。 然后将金属层连接在电铸装置的阴极位置,然后通孔连接器在通孔中电铸。