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71. 发明申请

US20160267998A1 MEMORY READ APPARATUS AND METHODS 有权
公开(公告)号：US20160267998A1
公开(公告)日：2016-09-15
申请号：US15162238
申请日：2016-05-23
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C16/26 , G11C11/56 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C11/5671 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/32
摘要： Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

72. 发明授权

US09378823B2 Programming a memory cell to a voltage to indicate a data value and after a relaxation time programming the memory cell to a second voltage to indicate the data value 有权
标题翻译：将存储器单元编程为电压以指示数据值，并且在松弛时间将存储器单元编程为第二电压以指示数据值
公开(公告)号：US09378823B2
公开(公告)日：2016-06-28
申请号：US14289816
申请日：2014-05-29
申请人： MICRON TECHNOLOGY, INC.
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/3459
摘要： A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is programmed to at least a second threshold voltage to indicate the particular data value. The second threshold voltage is greater than the first threshold voltage.
摘要翻译：存储器单元被编程为至少第一阈值电压以指示特定数据值。在等待放松时间之后，将存储单元编程为至少第二阈值电压以指示特定数据值。第二阈值电压大于第一阈值电压。

73. 发明授权

US09305656B2 Methods applying a non-zero voltage differential across a memory cell not involved in an access operation 有权
标题翻译：在不参与访问操作的存储器单元上应用非零电压差分的方法
公开(公告)号：US09305656B2
公开(公告)日：2016-04-05
申请号：US14625186
申请日：2015-02-18
申请人： MICRON TECHNOLOGY, INC.
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , G11C16/24 , G11C11/56 , G11C16/10 , G11C16/06 , G11C16/34
CPC分类号： G11C16/24 , G11C11/5621 , G11C16/06 , G11C16/10 , G11C16/349
摘要： Methods applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics.
摘要翻译：在不参与访问操作的存储器单元上应用非零电压差分的方法可以促进改进的数据保留特性。

74. 发明申请

US20160086666A1 MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE 有权
标题翻译：具有强大功能的阅读架构的内存阵列
公开(公告)号：US20160086666A1
公开(公告)日：2016-03-24
申请号：US14961042
申请日：2015-12-07
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C16/04 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/24 , G11C16/26
摘要： Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.
摘要翻译：各种实施例包括具有上弦和下弦的三维存储装置的装置和方法。上部串可以包括第一串存储器单元和基本上平行并彼此相邻布置的第二存储单元串。较低的串可以包括第三串存储器单元和基本上平行并彼此相邻布置的第四串存储单元。串可以各自具有耦合到其上的单独的读出放大器。第一和第三串以及第二和第四串可以被配置为在读取操作期间彼此串联耦合。描述附加的装置和方法。

75. 发明申请

US20160070663A1 SEQUENTIAL MEMORY ACCESS OPERATIONS 有权
公开(公告)号：US20160070663A1
公开(公告)日：2016-03-10
申请号：US14479703
申请日：2014-09-08
申请人： MICRON TECHNOLOGY, INC.
发明人： Toru Tanzawa
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F3/0604 , G06F3/0611 , G06F3/0625 , G06F3/0659 , G06F3/0679 , G06F12/06 , G06F12/0623 , G06F12/14 , G06F13/1657 , G06F13/1694 , G06F2212/1024 , G06F2212/1028 , G06F2212/1052 , G06F2212/214 , G06F2212/2532 , Y02D10/14
摘要： Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

76. 发明授权

US09177614B2 Apparatuses and methods including memory with top and bottom data lines 有权
标题翻译：装置和方法，包括具有顶部和底部数据线的存储器
公开(公告)号：US09177614B2
公开(公告)日：2015-11-03
申请号：US14444589
申请日：2014-07-28
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C5/06 , G11C5/02 , H01L27/115
CPC分类号： G11C5/063 , G11C5/025 , H01L27/11556 , H01L27/11582
摘要： Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.
摘要翻译：一些实施例包括具有第一组数据线，第二组数据线以及位于该装置的不同级别的存储单元的装置和方法。在这样的实施例中的至少一个中，存储器单元可以被布置在第一和第二组数据线之间的存储单元串中。描述包括附加装置和方法的其他实施例。

77. 发明申请

US20150287472A1 APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
标题翻译：用于控制存储器操作中的身体潜力的装置和方法
公开(公告)号：US20150287472A1
公开(公告)日：2015-10-08
申请号：US14746416
申请日：2015-06-22
申请人： Micron Technology, Inc.
发明人： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
IPC分类号： G11C16/32 , G11C16/04
CPC分类号： G11C16/3459 , G11C8/08 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3445 , G11C2213/71
摘要： Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
摘要翻译：一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。存储单元串包括与存储单元相关联的柱体。这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。描述其他实施例。

78. 发明申请

US20150243364A1 APPARATUSES AND METHODS INCLUDING MEMORY ARRAY DATA LINE SELECTION 有权
标题翻译：包括记忆阵列数据线选择的装置和方法
公开(公告)号：US20150243364A1
公开(公告)日：2015-08-27
申请号：US14709210
申请日：2015-05-11
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C16/04 , G11C16/0483 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11582
摘要： Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.
摘要翻译：一些实施例包括具有耦合到存储器单元串的数据线的装置和被配置为选择性地将数据线中的一个耦合到节点的选择器。存储单元串和选择器可以形成在设备的相同存储器阵列中。描述包括附加装置和方法的其它实施例。

79. 发明申请

US20150179273A1 MEMORY READ APPARATUS AND METHODS 有权
标题翻译：内存读取装置和方法
公开(公告)号：US20150179273A1
公开(公告)日：2015-06-25
申请号：US14639807
申请日：2015-03-05
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G11C16/26 , G11C16/32 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C11/5671 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/32
摘要： Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.
摘要翻译：公开了一种装置和方法，其包括将多条接入线路的电位提升到升高的电位的方法，其中每条接入线路与一串电荷存储装置的相应电荷存储装置相关联。所选择的一条接入线的电位降低，并且在所选择的接入线的电位降低的同时，感测与所选择的接入线相关联的电荷存储装置的数据状态。描述附加的装置和方法。

80. 发明申请

US20150155298A1 THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH 有权
标题翻译：具有减少接触长度的三维装置
公开(公告)号：US20150155298A1
公开(公告)日：2015-06-04
申请号：US14615830
申请日：2015-02-06
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： H01L27/115
CPC分类号： H01L27/108 , H01L21/74 , H01L27/0207 , H01L27/11 , H01L27/11531 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. Peripheral circuitry is formed on an elevated portion that is adjacent to the memory array and has an uppermost portion substantially coplanar with an uppermost surface of the memory array. Additional apparatuses and methods are described.
摘要翻译：各种实施例包括装置和方法，包括具有交替电平的半导体材料和电介质材料的存储器阵列，其具有在交替电平上形成的存储器单元串。一种这样的装置包括从衬底表面开始形成的存储器阵列。外围电路形成在与存储器阵列相邻的升高部分上，并且具有与存储器阵列的最上表面基本共面的最上部分。描述附加的装置和方法。

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