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71. 发明授权

US09040382B2 Selective epitaxial growth of semiconductor materials with reduced defects 有权
标题翻译：具有减少缺陷的半导体材料的选择性外延生长
公开(公告)号：US09040382B2
公开(公告)日：2015-05-26
申请号：US14319037
申请日：2014-06-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jing-Cheng Lin , Chen-Hua Yu
IPC分类号： H01L21/12 , H01L21/02 , H01L21/762 , H01L29/165 , H01L29/267
CPC分类号： H01L21/02494 , H01L21/02381 , H01L21/0245 , H01L21/02455 , H01L21/02532 , H01L21/02538 , H01L21/02587 , H01L21/02639 , H01L21/76224 , H01L29/165 , H01L29/267
摘要： A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.
摘要翻译：半导体器件包括由第一半导体材料形成的衬底; 基板上有两个绝缘子; 以及半导体区域，其具有在所述两个绝缘体之间并且在所述衬底上的部分。半导体区域具有与衬底接触并具有倾斜侧壁的底表面。半导体区域由与第一半导体材料不同的第二半导体材料形成。

72. 发明申请

US20150118840A1 Alignment Marks in Substrate Having Through-Substrate Via (TSV) 审中-公开
标题翻译：具有通过基底通孔（TSV）的基板中的对准标记
公开(公告)号：US20150118840A1
公开(公告)日：2015-04-30
申请号：US14586276
申请日：2014-12-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsin Chang , Fang Wen Tsai , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L23/49827 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2223/5442 , H01L2223/54426 , H01L2224/03002 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05647 , H01L2224/11002 , H01L2224/1146 , H01L2224/1147 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01327 , H01L2924/14 , H01L2924/04941 , H01L2924/04953 , H01L2924/00
摘要： A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
摘要翻译：一种器件包括衬底和包括穿透衬底的导电贯穿衬底通孔（TSV）的对准标记。

73. 发明申请

US20150102502A1 Integrated Fan-Out Structure with Openings in Buffer Layer 有权
标题翻译：在缓冲层中具有开口的集成扇出结构
公开(公告)号：US20150102502A1
公开(公告)日：2015-04-16
申请号：US14577450
申请日：2014-12-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wu Sen Chiu , Li-Hui Cheng , Po-Hao Tsai , Jing-Cheng Lin
IPC分类号： H01L23/48 , H01L25/10 , H01L23/31 , H01L21/56 , H01L21/768
CPC分类号： H01L23/315 , H01L21/268 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/6836 , H01L21/76802 , H01L23/3114 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/49827 , H01L23/544 , H01L24/17 , H01L24/19 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68372 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/0652 , H01L2225/06548 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2225/1082 , H01L2924/00014 , H01L2924/12042 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/82 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.
摘要翻译：包装包括模塑料，穿透模塑料的通孔，在模塑料中模制的模具，以及在模塑料上接触的缓冲层。开口通过缓冲层到通孔。缓冲层在与模制化合物和缓冲层之间的界面平行的平面中并且在开口的圆周周围具有波纹。其他实施例考虑了结合到包装的附加包装以及用于形成包装的方法。

74. 发明授权

US08994171B2 Method and apparatus for a conductive pillar structure 有权
标题翻译：导电柱结构的方法和装置
公开(公告)号：US08994171B2
公开(公告)日：2015-03-31
申请号：US13795081
申请日：2013-03-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung-Hua Chang , Cheng-Lin Huang , Nai-Wei Liu , Jui-Pin Hung , Jing-Cheng Lin
IPC分类号： H01L29/40 , H01L21/44 , H01L23/00
CPC分类号： H01L24/17 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L2224/0312 , H01L2224/03462 , H01L2224/03464 , H01L2224/0384 , H01L2224/0391 , H01L2224/0401 , H01L2224/05022 , H01L2224/05111 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05184 , H01L2224/05556 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/1112 , H01L2224/13017 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/15787 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.
摘要翻译：提供一种用于导电柱结构的方法和装置。可以提供一种器件，其可以包括衬底，在衬底上形成的第一钝化层，延伸穿过第一钝化层并进入衬底的导电互连，在第一钝化层上形成的导电焊盘，以及第二钝化层形成在互连焊盘和第二钝化层上。互连焊盘的一部分可以从第二钝化层露出。导电柱可以使用一个或多个无电镀工艺直接形成在互连焊盘上。导电柱可以具有第一宽度和第二宽度，第一高度对应于第一宽度和第二宽度之间的距离。

75. 发明申请

US20150069623A1 Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer 有权
标题翻译：集成扇出结构与缓冲层中的导向沟
公开(公告)号：US20150069623A1
公开(公告)日：2015-03-12
申请号：US14024311
申请日：2013-09-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Po-Hao Tsai , Feng-Cheng Hsu , Li-Hui Cheng , Jui-Pin Hung , Jing-Cheng Lin
IPC分类号： H01L23/31 , H01L21/56
CPC分类号： H01L25/105 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76802 , H01L21/7682 , H01L21/8221 , H01L23/31 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L24/19 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/117 , H01L25/50 , H01L2221/68327 , H01L2221/68372 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2225/1082 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2224/82 , H01L2224/83 , H01L2924/00
摘要： A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
摘要翻译：底部包装包括模制化合物，在模制化合物上方并与之接触的缓冲层，以及穿过模塑料的穿通孔。在模塑料中模制器件模具。引导沟槽从缓冲层的顶表面延伸到缓冲层中，其中引导沟槽与器件裸片不对准。

76. 发明申请

US20140346665A1 Integrated Circuit Structure and Method for Reducing Polymer Layer Delamination 有权
标题翻译：集成电路结构和降低聚合物层分层的方法
公开(公告)号：US20140346665A1
公开(公告)日：2014-11-27
申请号：US13901311
申请日：2013-05-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jing-Cheng Lin , Jui-Pin Hung , Hsien-Wen Liu , Min-Chen Lin
IPC分类号： H01L23/498 , H01L23/522 , H01L21/768
CPC分类号： H01L25/50 , H01L21/56 , H01L21/568 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L23/49811 , H01L23/525 , H01L23/5329 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L24/81 , H01L25/065 , H01L2224/0401 , H01L2224/04105 , H01L2224/05027 , H01L2224/05166 , H01L2224/05582 , H01L2224/05647 , H01L2224/11013 , H01L2224/1134 , H01L2224/1148 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/96 , H01L2924/181 , H01L2924/18162 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2924/00 , H01L2924/014
摘要： An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
摘要翻译：实施例集成电路结构包括衬底，衬底上的金属焊盘，在衬底上方并电连接到金属焊盘的钝化后互连（PPI）结构，PPI结构上的第一聚合物层，凸块下冶金（ UBM）延伸到第一聚合物层中的开口并且电连接到PPI结构，以及在与UBM相邻的第一聚合物层的顶表面上的阻挡层。

77. 发明申请

US20140339697A1 Solder Bump for Ball Grid Array 审中-公开
标题翻译：用于球栅阵列的焊球
公开(公告)号：US20140339697A1
公开(公告)日：2014-11-20
申请号：US14451271
申请日：2014-08-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung-Hua Chang , Cheng-Lin Huang , Jing-Cheng Lin
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L23/49816 , H01L24/11 , H01L2224/118 , H01L2224/13 , H01L2224/13016 , H01L2224/131 , H01L2224/1319 , H01L2924/01029 , H01L2924/014 , H01L2924/06 , H01L2924/0665 , H01L2924/15788 , H01L2924/37001 , H01L2924/00
摘要： A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
摘要翻译：用于球栅阵列（BGA）的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属（UBM）层和焊料凸块。焊料凸块具有凸块宽度和凸块高度，并且凸块高度比凸块宽度的比值小于1。

78. 发明授权

US08877554B2 Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices 有权
标题翻译：封装半导体器件，封装半导体器件的方法和PoP器件
公开(公告)号：US08877554B2
公开(公告)日：2014-11-04
申请号：US13890162
申请日：2013-05-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Po-Hao Tsai , Jui-Pin Hung , Jing-Cheng Lin
IPC分类号： H01L23/48 , H01L23/498 , H01L21/768
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L21/78 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/03 , H01L24/19 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/02317 , H01L2224/033 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/19 , H01L2224/32145 , H01L2224/32225 , H01L2224/73265 , H01L2224/73267 , H01L2224/8392 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1047 , H01L2225/1058 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2224/48227 , H01L2924/00012 , H01L2224/82 , H01L2924/00 , H01L2224/83 , H01L2224/83005
摘要： Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads.
摘要翻译：公开了封装半导体器件，封装半导体器件的方法和封装封装（PoP）器件。在一些实施例中，封装半导体器件的方法包括在载体上形成贯穿封装通孔（TPV），以及将半导体器件耦合到载体。半导体器件包括设置在其表面上的接触焊盘和设置在接触焊盘上的绝缘材料。在TPV和半导体器件之间的载体上形成模制材料。使用在接触焊盘上的激光钻孔工艺在绝缘材料中形成开口，并且在绝缘材料和绝缘材料中的开口上形成再分布层（RDL）。 RDL的一部分耦合到每个接触焊盘的顶表面。

79. 发明授权

US08847389B1 Method and apparatus for a conductive bump structure 有权
标题翻译：导电凸块结构的方法和装置
公开(公告)号：US08847389B1
公开(公告)日：2014-09-30
申请号：US13889053
申请日：2013-05-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung-Hua Chang , Cheng-Lin Huang , Jing-Cheng Lin
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L23/49816 , H01L23/481 , H01L23/49827 , H01L23/49894 , H01L2224/13
摘要： A method and apparatus for a conductive bump structure is provided. The conductive bump structure may include a conductive layer and a conductive bump formed over a through via (“TV”). The TV may be formed through a substrate and a passivation layer. The TV may have a top surface extending above a top surface of the passivation layer. The conductive layer may be formed directly over the TV using one or more electroless plating processes. The conductive layer may have sides that may taper from a top surface of the conductive layer to the top surface of the passivation layer. The conductive layer may include a plurality of layers, wherein each layer may be formed using one or more electroless plating processes. The conductive bump may be formed on the conductive layer and may be reflowed to couple the conductive bump to the conductive layer.
摘要翻译：提供了一种用于导电凸块结构的方法和装置。导电凸块结构可以包括在通孔（“TV”）上形成的导电层和导电凸块。 TV可以通过衬底和钝化层形成。 TV可以具有在钝化层的顶表面上方延伸的顶表面。可以使用一个或多个无电镀方法直接在电视机上形成导电层。导电层可以具有可以从导电层的顶表面到钝化层的顶表面逐渐变细的侧面。导电层可以包括多个层，其中每个层可以使用一个或多个无电镀方法形成。导电凸块可以形成在导电层上，并且可以被回流以将导电凸块耦合到导电层。

80. 发明申请

US20140287581A1 Through Silicon Via with Embedded Barrier Pad 审中-公开
标题翻译：通过硅通道与嵌入式障碍垫
公开(公告)号：US20140287581A1
公开(公告)日：2014-09-25
申请号：US14299886
申请日：2014-06-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yung-Chi Lin , Sylvia Lo , Jing-Cheng Lin , Yen-Hung Chen , Wen-Chih Chiou
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/7685 , H01L21/76877 , H01L23/481 , H01L24/03 , H01L24/05 , H01L2224/0346 , H01L2224/03616 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05025 , H01L2224/05026 , H01L2224/05099 , H01L2224/05155 , H01L2224/05157 , H01L2224/05166 , H01L2224/05181 , H01L2224/05541 , H01L2224/05571 , H01L2224/05599 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2924/00014 , H01L2924/00012 , H01L2924/207 , H01L2224/05552
摘要： A system and method are disclosed for providing a through silicon via (TSV) with a barrier pad deposited below the top surface of the TSV, the top surface having reduced topographic variations. A bottom TSV pad is deposited into a via and then polished so the top surface is below the substrate top surface. A barrier pad is then deposited in the via, and a top TSV pad deposited on the barrier pad. The top TSV barrier pad is polished to bring the top surface of the top TSV pad about level with the substrate. The barrier pad may be less than about 1 microns thick, and the top TSV pad may be less than about 6 microns thick. The barrier pad may be a dissimilar metal from the top and bottom TSV pads, and may be selected from a group comprising titanium, tantalum, cobalt, nickel and the like.
摘要翻译：公开了一种用于向TSV提供沉积在TSV的顶表面下方的阻挡层的系统和方法，顶表面具有减小的地形变化。将底部TSV焊盘沉积到通孔中，然后抛光，使得顶表面在衬底顶表面下方。然后在通孔中沉积阻挡层，并且沉积在阻挡层上的顶部TSV焊盘。顶部的TSV屏障垫被抛光，以使顶部TSV焊盘的顶部表面与衬底的高度一致。阻挡垫可以小于约1微米厚，并且顶部TSV垫可以小于约6微米厚。阻挡垫可以是来自顶部和底部TSV垫的不同金属，并且可以选自包括钛，钽，钴，镍等的组。

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