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71. 发明申请

US20180175157A1 METHOD FOR AVOIDING IL REGROWN IN A HKMG PROCESS 审中-公开
公开(公告)号：US20180175157A1
公开(公告)日：2018-06-21
申请号：US15429192
申请日：2017-02-10
申请人： Shanghai Huali Microelectronics Corporation
发明人： Yingming Liu , Yu Bao , Haifeng Zhou , Jingxun Fang
IPC分类号： H01L29/51 , H01L29/423 , H01L21/28 , H01L21/02 , H01L29/66 , H01L29/78
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28229 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

72. 发明申请

US20180174924A1 FABRICATION TECHNOLOGY FOR METAL GATE 审中-公开
公开(公告)号：US20180174924A1
公开(公告)日：2018-06-21
申请号：US15429195
申请日：2017-02-10
申请人： Shanghai Huali Microelectronics Corporation
发明人： Tong Lei , Yongyue Chen , Haifeng Zhou
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L21/02 , H01L21/321 , H01L21/033
CPC分类号： H01L21/823828 , H01L21/02115 , H01L21/02167 , H01L21/0332 , H01L21/3212 , H01L21/823842 , H01L27/0922 , H01L29/66545
摘要： One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.

73. 发明授权

US09680023B1 Method of manufacturing a dual-gate FinFET 有权
公开(公告)号：US09680023B1
公开(公告)日：2017-06-13
申请号：US15235124
申请日：2016-08-12
申请人： Yu Bao
发明人： Yu Bao
IPC分类号： H01L27/108 , H01L29/78 , H01L29/40 , H01L29/66
CPC分类号： H01L29/7855 , H01L29/401 , H01L29/66545 , H01L29/66795
摘要： A method of manufacturing a dual-gate FinFET is provided. The method includes: forming a fin structure on the semiconductor substrate, depositing an oxide layer and planarizing until the top of the fin structure is exposed, depositing a hard mask layer and patterning, preforming a first etch back process to one side of the oxide layer, and then removing the rest of the hard mask layer, preforming a second etch back process to the oxide layers at both sides of the fin structure simultaneously, forming a gate dielectric layer on surface of the fin structure, then depositing gate material on the gate dielectric layer and patterning, removing gate material on top of the fin structure, forming a drive gate and a control gate at two sides of the fin structure respectively; wherein height of the control gate is higher than height of the drive gate.

74. 发明授权

US09390915B1 Methods and systems for improved uniformity of SiGe thickness 有权
标题翻译：提高SiGe厚度均匀性的方法和系统
公开(公告)号：US09390915B1
公开(公告)日：2016-07-12
申请号：US14691520
申请日：2015-04-20
申请人： Shanghai Huali Microelectronics Corporation
发明人： Quanbo Li , Jun Huang , Xiangguo Meng
IPC分类号： H01L21/762 , H01L21/02 , H01L21/311 , H01L21/66
CPC分类号： H01L21/02532 , H01L21/0206 , H01L21/02115 , H01L21/02118 , H01L21/02282 , H01L21/3086 , H01L21/31111 , H01L21/31133 , H01L21/76224 , H01L21/76232 , H01L22/26 , H01L29/165 , Y02P80/30
摘要： A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a Silicon (Si)-shallow trench isolation (STI) substrate. A selective coverage is provided to protect the height of the Si-STI substrate and an Si-STI interface. A desirable geometry can be obtained for forming a silicon germanium (SiGe)layer with uniform thickness near the divot.
摘要翻译：一种方法用于形成保护层以覆盖半导体材料的两个区域之间的凹陷。在蚀刻过程中，保护层保护纹理被蚀刻掉，并减少硅（Si） - 浅沟槽隔离（STI）衬底的材料损失。提供选择性覆盖以保护Si-STI衬底和Si-STI界面的高度。可以获得期望的几何形状，用于形成具有均匀厚度的硅锗（SiGe）层。

75. 发明授权

US09171731B2 Method of forming the gate with the LELE double pattern 有权
标题翻译：用LELE双重图案形成门的方法
公开(公告)号：US09171731B2
公开(公告)日：2015-10-27
申请号：US14085380
申请日：2013-11-20
申请人： Shanghai Huali Microelectronics Corporation
发明人： Jun Huang , ZhiBiao Mao , QuanBo Li , ZhiFeng Gan , RunLing Li
IPC分类号： H01L21/302 , H01L21/306 , H01L21/28 , H01L21/033 , H01L21/3213 , H01L21/308
CPC分类号： H01L21/306 , H01L21/0337 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/32139
摘要： The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.
摘要翻译：本发明涉及微电子技术，更具体地说，涉及一种用LELE双重图案形成门的方法。该方法采用ONO结构（Oxide-SiN-Oxide）。 ONO结构暴露两次，并且在多晶硅蚀刻的处理中使用先进的图案化膜作为掩模。 ONO结构用于替代传统的氧化硅硬掩模，以及基于旋涂的ODL（有机底层）的底层结构和SHB（Si基硬掩模）的中间层结构。该方法节省了成本，并改进了高级图案化膜作为掩模的过程，其中40nm及以上的节点被应用于具有22/20nm及以下的节点的过程。因此，22/20nm及以下节点的多晶硅栅极的成熟度和稳定性得到改善。

76. 发明授权

US09123619B2 Method for inhibiting the electric crosstalk of back illuminated CMOS image sensor 有权
标题翻译：抑制背照式CMOS图像传感器的电串扰的方法
公开(公告)号：US09123619B2
公开(公告)日：2015-09-01
申请号：US14098017
申请日：2013-12-05
申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION
发明人： Zhi Tian , QiuMin Jin
IPC分类号： H01L21/00 , H01L27/146
CPC分类号： H01L27/14689 , H01L27/14609
摘要： The present invention discloses a method for inhibiting the electric crosstalk of back illuminated CMOS image sensor. This invention comprises, two ion implanting layers are implanted at the different area of the backside of the pixel unit after the thickness of the backside of CMOS image sensor is reduced. The ion concentrations implanted into the two layers are controlled to decrease progressively from top to bottom. An electric field is formed from top to bottom inside the epitaxial layer. The said electric field absorbs the incident light which arrives at the substrate region outside of the space charge of the photodiode. It reduces the electron diffuses in different pixels. Consequently, it reduces the electric crosstalk of pixels, improves the manufacture process and improve the image quality of the of CMOS image sensor.
摘要翻译：本发明公开了一种抑制背照式CMOS图像传感器的电串扰的方法。本发明包括：在CMOS图像传感器的背面的厚度减小之后，将两个离子注入层注入到像素单元的背面的不同区域。控制注入两层的离子浓度从上到下逐渐降低。在外延层内部从上到下形成电场。所述电场吸收到达光电二极管的空间电荷之外的衬底区域的入射光。它可以减少不同像素的电子扩散。因此，它减少了像素的电串扰，改善了CMOS图像传感器的制造工艺和图像质量。

77. 发明授权

US09110126B2 Method for measuring interface state density 有权
标题翻译：测量界面状态密度的方法
公开(公告)号：US09110126B2
公开(公告)日：2015-08-18
申请号：US13656701
申请日：2012-10-20
申请人： Yongfeng Cao
发明人： Yongfeng Cao
IPC分类号： G01R27/00 , G01R31/26 , H01L21/66
CPC分类号： G01R31/2639 , G01R31/2648 , H01L22/14
摘要： The present invention provides a method for measuring the interface state density by a conductance technique. In particular, the method comprises: biasing a MOS capacitor structure to be measured in an accumulation region, measuring the MOS capacitor structure under a fixed bias voltage and at predetermined scanning frequencies in the accumulation region by using a Gp-G model, and calculating the values of the series resistor at respective predetermined scanning frequencies to obtain a series resistor model; obtaining an accurate model in an inversion region from the series resistor model varying with the predetermined scanning frequencies obtained in the accumulation region and obtaining the measurement results of interface state according to the accurate model.
摘要翻译：本发明提供一种通过电导技术测量界面态密度的方法。特别地，该方法包括：通过使用Gp-G模型，在积累区域中偏置待测量的MOS电容器结构，在固定偏置电压和累积区域中的预定扫描频率下测量MOS电容器结构，各个预定扫描频率下的串联电阻器的值，以获得串联电阻器模型; 在从在累积区域获得的预定扫描频率变化的串联电阻器模型的反转区域中获得准确的模型，并根据准确的模型获得界面状态的测量结果。

78. 发明授权

US09076668B2 Method of manufacturing the trench of U-shape 有权
标题翻译：制造U型沟槽的方法
公开(公告)号：US09076668B2
公开(公告)日：2015-07-07
申请号：US14070060
申请日：2013-11-01
申请人： Shanghai Huali Microelectronics Corporation
发明人： XuBin Jing , Fang Li , WenYan Liu
IPC分类号： H01L21/8238 , H01L29/08 , H01L29/66 , H01L21/4757 , H01L27/092
CPC分类号： H01L29/0847 , H01L21/47576 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/092 , H01L29/66477 , H01L29/66636 , H01L29/78
摘要： The present invention relates to the manufacture of CMOS semiconductor device. This invention includes: Step S1, a layer of silicon oxide is deposited covering the surface of the polysilicon gates and the exposed upper surface of the silicon substrate, the silicon oxide layer is removed on the upper surface of the exposed silicon substrate, and then the barrier layer is formed at the surface of the polysilicon gates; Step S2, the ions are implanted into the exposed substrate, and then several doped silicon regions are formed in the silicon substrate; Step S3, the doped silicon regions are etched to form the trench of U-shape, then the barrier layer is removed. The present invention protects the polysilicon gate and the substrate during the process of forming the trench. The rate of etching is increased and the productivity is improved and it is possible to control the depth of the U-shaped trench.
摘要翻译：本发明涉及CMOS半导体器件的制造。本发明包括：步骤S1，沉积覆盖多晶硅栅极的表面和硅衬底的暴露的上表面的氧化硅层，在暴露的硅衬底的上表面上去除氧化硅层，然后阻挡层形成在多晶硅栅极的表面; 步骤S2，将离子注入暴露的衬底中，然后在硅衬底中形成多个掺杂的硅区; 步骤S3，蚀刻掺杂的硅区域以形成U形沟槽，然后去除阻挡层。本发明在形成沟槽的过程中保护多晶硅栅极和衬底。蚀刻速率提高，生产率提高，并且可以控制U形沟槽的深度。

79. 发明授权

US08987013B2 Method of inspecting misalignment of polysilicon gate 有权
标题翻译：检查多晶硅栅极未对准的方法
公开(公告)号：US08987013B2
公开(公告)日：2015-03-24
申请号：US14142584
申请日：2013-12-27
申请人： Shanghai Huali Microelectronics Corporation
发明人： Rongwei Fan , Hunglin Chen , Yin Long , Qiliang Ni
IPC分类号： H01L21/66 , G01R31/307
CPC分类号： H01L22/14 , G01R31/307 , H01L22/12 , H01L22/30 , H01L22/34
摘要： A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection tool operating with a positive mode to carry out electrical defect inspection. The method can be applied in precisely figuring out the in-plane misalignment of the polysilicon gates of an in-process semiconductor product and identifying a misalignment tendency therebetween across a wafer by verifying all locations of interest thereon, thus providing a methodology for process window optimization and on-line monitoring and contributing to the manufacturing process and yield improvement.
摘要翻译：公开了一种检查多晶硅栅极未对准的方法，其特征在于在测试晶片中仅在P阱中形成NMOS器件，并利用以正模式工作的先进电子束检查工具进行电气缺陷检查。该方法可以应用于精确地计算过程中半导体产品的多晶硅栅极的面内未对准，并通过验证其上感兴趣的所有位置来识别晶片之间的偏移趋势，从而提供了用于处理窗口优化的方法并在线监测并有助于制造过程和产量的提高。

80. 发明申请

US20150017814A1 METHOD OF FORMING GATE OXIDE LAYER 审中-公开
标题翻译：形成氧化铝层的方法
公开(公告)号：US20150017814A1
公开(公告)日：2015-01-15
申请号：US14084012
申请日：2013-11-19
申请人： Shanghai Huali Microelectronics Corporation
发明人： Hongwei ZHANG , Shu Koon PANG
IPC分类号： H01L21/28
CPC分类号： H01L21/28185 , H01L21/268 , H01L21/28202
摘要： A method of forming a gate oxide layer is disclosed, which introduces a rapid laser annealing process, performed on the surface of the gate SiON layer, prior to a high-temperature annealing process performed on the gate SiON layer. This enables the method of the invention to remove the intrinsic oxide layer, protect the doped nitrogen atoms from the adverse influence of organic absorption, and lead to the formation of an amorphized surface layer which is able to prevent nitrogen atoms located around the surface from escaping by volatilization and nitrogen atoms beneath the surface from diffusing towards the SiO2/Si boundary. Therefore, the gate SiON layer formed by the method of the invention can ensure a high and stable nitrogen content, thus achieving the objective to obtain a gate SiON layer with a more precisely trimmed dielectric constant and hence improve the electrical properties of the semiconductor device being fabricated.
摘要翻译：公开了一种形成栅极氧化层的方法，其中在栅极SiON层进行高温退火处理之前，对栅极SiON层的表面进行快速激光退火处理。这使得本发明的方法能够去除本征氧化物层，保护掺杂氮原子免受有机吸收的不利影响，并导致形成非晶化表面层，其能够防止位于表面周围的氮原子逸出通过表面下方的挥发和氮原子向SiO 2 / Si界面扩散。因此，通过本发明的方法形成的栅极SiON层可以确保高且稳定的氮含量，从而达到获得具有更精确修整的介电常数的栅极SiON层的目的，并因此提高半导体器件的电性能制造。

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