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71. 发明申请

US20130299884A1 MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE 审中-公开
标题翻译：用于制造存储器件的存储器件和方法
公开(公告)号：US20130299884A1
公开(公告)日：2013-11-14
申请号：US13468797
申请日：2012-05-10
申请人： Shian Jyh Lin , Jen Jui Huang
发明人： Shian Jyh Lin , Jen Jui Huang
IPC分类号： H01L29/772 , H01L21/02
CPC分类号： H01L21/76224 , H01L27/10876 , H01L27/10891
摘要： A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area having source and drain regions. The first and second trench isolations extend parallel to each other. The line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area and is formed in the substrate adjacent to the first trench isolation defining a first segment of the active area with the first trench isolation. The second word line extends across the active area and is formed in the substrate adjacent to the second trench isolation defining a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.
摘要翻译：存储器件包括衬底，第一和第二沟槽隔离，多个线型隔离，第一字线和第二字线。衬底包括具有源区和漏区的有源区。第一和第二沟槽隔离物彼此平行延伸。线型隔离定义了有源区以及第一和第二沟槽隔离。第一字线延伸穿过有效区域，并且形成在邻近第一沟槽隔离物的衬底中，限定具有第一沟槽隔离的有源区域的第一段。第二字线延伸穿过有效区域并且形成在与第二沟槽隔离件相邻的衬底中，限定具有第二沟槽隔离的有源区域的第二段。第一段的大小基本上等于第二段的大小。

72. 发明申请

US20130299881A1 ASYMMETRIC WEDGE JFET, RELATED METHOD AND DESIGN STRUCTURE 失效
标题翻译：非对称楔形结构，相关方法和设计结构
公开(公告)号：US20130299881A1
公开(公告)日：2013-11-14
申请号：US13870286
申请日：2013-04-25
申请人： International Business Machines Corporation
发明人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
IPC分类号： H01L29/772 , G06F17/50
CPC分类号： H01L29/772 , G06F17/50 , H01L29/0649 , H01L29/0843 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.
摘要翻译：提供了一种用于集成电路（IC）芯片的结栅场效应晶体管（JFET），其包括源极区，漏极区，下栅极和沟道，其中绝缘浅沟槽隔离（STI）区域从源区域的上表面的内边缘到漏极区域的上表面的内边缘，而没有有意掺杂的区域，例如上栅极，与源极/漏极区域之间的IC芯片的上表面共面。此外，可以包括设置在STI区域的一部分下方的不对称的准掩埋的上栅极，但不在靠近漏极区域的STI区域的一部分下方延伸。本发明的实施例还包括在源极区域下提供注入层以减少Ron。还公开了相关的方法和设计结构。

73. 发明申请

US20130277746A1 INTEGRATED CIRCUITS HAVING PROTRUDING SOURCE AND DRAIN REGIONS AND METHODS FOR FORMING INTEGRATED CIRCUITS 有权
标题翻译：具有推广来源和排水区域的集成电路和形成集成电路的方法
公开(公告)号：US20130277746A1
公开(公告)日：2013-10-24
申请号：US13454433
申请日：2012-04-24
申请人： Tim Baldauf , Tom Herrmann , Stefan Flachowsky , Ralf Illgen
发明人： Tim Baldauf , Tom Herrmann , Stefan Flachowsky , Ralf Illgen
IPC分类号： H01L27/088 , H01L21/283 , H01L29/772 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/76882 , H01L21/76897 , H01L21/823814 , H01L21/823821 , H01L29/165 , H01L29/66545 , H01L29/7848
摘要： Methods for forming integrated circuits and integrated circuits are disclosed. The integrated circuits comprise gate structures overlying and transverse to one or more fins that are delineated by trenches formed in a semiconductor substrate. Protruding portions are formed in the trenches in between the gate electrode structure on exposed sidewall surfaces of the one or more fins. The trenches are filled with an insulating material between the protruding portions and the gate structures.
摘要翻译：公开了用于形成集成电路和集成电路的方法。集成电路包括覆盖并横向于由形成在半导体衬底中的沟槽描绘的一个或多个鳍的栅极结构。凸起部分形成在一个或多个翅片的暴露侧壁表面上的栅电极结构之间的沟槽中。沟槽在突出部分和栅极结构之间填充有绝缘材料。

74. 发明申请

US20130270611A1 SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS 有权
标题翻译：具有反射面的源和漏极的半导体结构
公开(公告)号：US20130270611A1
公开(公告)日：2013-10-17
申请号：US13446350
申请日：2012-04-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/02579 , H01L21/02609 , H01L21/84 , H01L29/0657 , H01L29/0847 , H01L29/78
摘要： A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
摘要翻译：包括半导体晶片的半导体结构。所述半导体晶片包括栅极结构，所述半导体晶片中与所述栅极结构的第一侧相邻的第一沟槽和与所述栅极结构的第二侧相邻的第二沟槽，所述第一和第二沟槽填充有掺杂的外延硅，在填充的第一沟槽中形成源极，并且在填充的第二沟槽中形成漏极，使得源极和漏极中的每一个凹入并具有倒置的面。在优选的示例性实施例中，外延硅掺杂有硼。

75. 发明申请

US20130264612A1 DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP 有权
标题翻译：用于形成具有可控接合深度和横向覆盖的夏普延伸区域的装置和方法
公开(公告)号：US20130264612A1
公开(公告)日：2013-10-10
申请号：US13440546
申请日：2012-04-05
申请人： Isaac Lauer , Effendi Leobandung , Ghavam G. Shahidi
发明人： Isaac Lauer , Effendi Leobandung , Ghavam G. Shahidi
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L29/66492 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method for forming a semiconductor device includes forming a gate stack on a monocrystalline substrate. A surface of the substrate adjacent to the gate stack and below a portion of the gate stack is amorphorized. The surface is etched to selectively remove a thickness of amorphorized portions to form undercuts below the gate stack. A layer is epitaxially grown in the thickness and the undercuts to form an extension region for the semiconductor device. Devices are also provided.
摘要翻译：一种用于形成半导体器件的方法包括在单晶衬底上形成栅叠层。衬底的与栅极堆叠相邻并且栅极堆叠的一部分下方的表面是无定形的。蚀刻表面以选择性去除非晶化部分的厚度，以在栅极堆叠下方形成底切。在厚度和底切上外延生长层，以形成用于半导体器件的延伸区域。还提供设备。

76. 发明授权

US08536629B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08536629B2
公开(公告)日：2013-09-17
申请号：US13202687
申请日：2010-01-14
申请人： Munehiro Tada , Hiromitsu Hada
发明人： Munehiro Tada , Hiromitsu Hada
IPC分类号： H01L29/772 , H01L21/762
CPC分类号： H01L21/8221 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/31633 , H01L21/76254 , H01L25/0657 , H01L27/0688 , H01L27/108 , H01L27/10802 , H01L27/10897 , H01L27/1203 , H01L27/124 , H01L27/1266 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/0002 , H01L2924/12044 , H01L2924/00 , H01L2224/80001
摘要： A method for manufacturing a semiconductor device, includes: forming an insulating film containing silicon, oxygen and carbon on at least one of a first substrate and a second substrate; and bonding the first substrate and the second substrate together, with the insulating film interposed therebetween. There can be provided a method capable of manufacturing a semiconductor device having high element density, high performance and high reliability, with high yield.
摘要翻译：一种制造半导体器件的方法，包括：在第一衬底和第二衬底中的至少一个上形成含有硅，氧和碳的绝缘膜; 以及将所述第一基板和所述第二基板接合在一起，并且所述绝缘膜插入其间。可以提供能够以高产率制造元件密度高，性能高，可靠性高的半导体器件的方法。

77. 发明申请

US20130228831A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF 有权
标题翻译：半导体结构及其制造工艺
公开(公告)号：US20130228831A1
公开(公告)日：2013-09-05
申请号：US13411890
申请日：2012-03-05
申请人： Yu-Hsien Chin , Chih-Chia Hsu , Yin-Fu Huang
发明人： Yu-Hsien Chin , Chih-Chia Hsu , Yin-Fu Huang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66477 , H01L29/0878 , H01L29/1087 , H01L29/401 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.
摘要翻译：半导体结构包括具有第一导电类型的衬底，在衬底中形成的第二导电类型的阱，形成在阱中的第一掺杂区和第二掺杂区，场氧化物，第一电介质层和第二电介质层。场氧化物形成在阱的表面区域和第一掺杂区域与第二掺杂区域之间。第一电介质层形成在阱的表面区域上并覆盖场氧化物的边缘部分。第一介电层具有第一厚度。第二电介质层形成在阱的表面区域上。第二电介质层的第二厚度小于第一厚度。

78. 发明授权

US08525239B2 Semiconductor device and method for driving same 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08525239B2
公开(公告)日：2013-09-03
申请号：US13390613
申请日：2011-05-24
申请人： Koutarou Tanaka , Takashi Hori , Kazuhiro Adachi
发明人： Koutarou Tanaka , Takashi Hori , Kazuhiro Adachi
IPC分类号： H01L29/772
CPC分类号： H01L29/7838 , H01L29/1033 , H01L29/1608 , H01L29/7828
摘要： The present invention is directed to an MIS type semiconductor device, including a channel layer between a semiconductor body region and a gate insulating film, the channel layer having an opposite semiconductor polarity to that of the semiconductor body region. Since Vfb of the semiconductor device is equivalent to or less than a gate rated voltage Vgcc− of the semiconductor device with respect to an OFF-polarity, density of carrier charge that is induced near the surface of the semiconductor body region is kept at a predetermined amount or less with a guaranteed range of operation of the semiconductor device.
摘要翻译：本发明涉及一种MIS半导体器件，其包括在半导体主体区域和栅极绝缘膜之间的沟道层，沟道层具有与半导体本体区域相反的半导体极性。由于半导体器件的Vfb相对于OFF极性等于或小于半导体器件的栅极额定电压Vgcc-，所以在半导体本体区域的表面附近感应的载流子电荷的密度保持在预定的数量或更少，具有半导体器件的有保证的操作范围。

79. 发明申请

US20130207166A1 Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition 有权
标题翻译：掺杂SiGe源/漏极应力沉积的方法和装置
公开(公告)号：US20130207166A1
公开(公告)日：2013-08-15
申请号：US13371177
申请日：2012-02-10
申请人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
发明人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0257 , H01L21/02579 , H01L21/02639 , H01L29/0847 , H01L29/167 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device system, structure and method of manufacture of a source/drain with SiGe stressor material to address effects due to dopant out-diffusion are disclosed. In an embodiment, a semiconductor substrate is provided with a gate structure, and recesses for source and drain are formed on opposing sides of the gate structure. Doped stressors are embedded into the recessed source and drain regions, and a plurality of layers of undoped stressor, lightly doped stressor, highly doped stressor, and a cap layer are formed in an in-situ epitaxial process. In another embodiment the doped stressor material is boron doped epitaxial SiGe. In an alternative embodiment an additional layer of undoped stressor material is formed.
摘要翻译：公开了一种利用SiGe应力材料制造源极/漏极的半导体器件系统，结构和方法，以解决由掺杂剂扩散引起的影响。在一个实施例中，半导体衬底设置有栅极结构，并且用于源极和漏极的凹槽形成在栅极结构的相对侧上。掺杂的应力源嵌入到凹陷的源极和漏极区域中，并且在原位外延工艺中形成多层未掺杂的应力源，轻掺杂应力源，高掺杂应力源和覆盖层。在另一个实施例中，掺杂应力源材料是硼掺杂的外延SiGe。在替代实施例中，形成附加的未掺杂应力源材料层。

80. 发明申请

US20130134486A1 Methods of Patterning Features in a Structure Using Multiple Sidewall Image Transfer Technique 有权
标题翻译：使用多边墙图像传输技术的结构中图形特征的方法
公开(公告)号：US20130134486A1
公开(公告)日：2013-05-30
申请号：US13305303
申请日：2011-11-28
申请人： Nicholas V. LiCausi
发明人： Nicholas V. LiCausi
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/0337 , H01L21/28132 , H01L21/3086 , H01L21/32139 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure.
摘要翻译：本文公开了使用多侧壁图像转移技术在结构中形成特征的方法，例如用于形成集成电路器件或半导体衬底的材料层。在一个示例中，该方法包括在结构之上形成第一心轴，形成与第一心轴相邻的多个第一间隔件，邻近第一间隔件之一形成多个第二心轴，并且形成多个第二间隔件，第二个心轴该方法还包括执行至少一个蚀刻工艺，以相对于第一间隔件和第二间隔件选择性地移除第一心轴和第二心轴，从而限定由第一间隔件和第二间隔件组成的蚀刻掩模，并执行至少一个蚀刻通过结构上的蚀刻掩模处理以在结构中限定多个特征。

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