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71. 发明申请

US20120104550A1 HIGH ASPECT RATIO CONTACTS 审中-公开
标题翻译：高等效比联系
公开(公告)号：US20120104550A1
公开(公告)日：2012-05-03
申请号：US13347192
申请日：2012-01-10
申请人： Aaron R. Wilson
发明人： Aaron R. Wilson
IPC分类号： H01L27/108 , H01L29/92
CPC分类号： H01L21/31116 , H01L21/31105 , H01L21/31127 , H01L21/31138
摘要： A contact formed in accordance with a process for etching a insulating material to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating material to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating material is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1,where the first gaseous etchant has a lower molecular weight than the second gaseous etchant.
摘要翻译：根据用于蚀刻绝缘材料以产生具有至少15:1的纵横比的开口的方法形成的触点，首先将绝缘材料暴露于包含Ar，Xe的第二气态蚀刻剂的第二等离子体及其组合以形成长宽比小于15:1的开口。其次，将绝缘材料暴露于具有至少50％氦（He）的第一气态蚀刻剂的第一等离子体，以蚀刻具有至少15:1的纵横比的开口，从而将纵横比增加到大于15： 1，其中第一气体蚀刻剂具有比第二气体蚀刻剂更低的分子量。

72. 发明授权

US08169014B2 Interdigitated capacitive structure for an integrated circuit 有权
标题翻译：用于集成电路的交叉电容结构
公开(公告)号：US08169014B2
公开(公告)日：2012-05-01
申请号：US11328502
申请日：2006-01-09
申请人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.
摘要翻译：用于集成电路的改进的互指电容结构的系统和方法。优选实施例包括基本上平行的叉指序列序列的第一层，每个条带具有第一极性或第二极性，该序列在第一极性的条带和第二极性的条之间交替。第一介电层沉积在第一层条带的每条上。基本上交错的延伸条的序列的第一延伸层沉积在第一介电层上，每个延伸条沉积在具有相反极性的第一层的条上。通孔的第一序列耦合到第一延伸层，每个通孔沉积在相同极性的延伸条上。基本上平行的叉指序列序列的第二层可以耦合到第一序列通孔。

73. 发明申请

US20120098045A1 Zero Temperature Coefficient Capacitor 有权
标题翻译：零温度系数电容器
公开(公告)号：US20120098045A1
公开(公告)日：2012-04-26
申请号：US13267674
申请日：2011-10-06
申请人： Weidong Tian , Imran Khan
发明人： Weidong Tian , Imran Khan
IPC分类号： H01L29/772 , H01L21/336 , H01L29/92
CPC分类号： H01L28/40 , H01L27/0629 , H01L29/94
摘要： A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.
摘要翻译：零温度系数（ZTC）电容器，其包括磷密度在1.7×1020原子/ cm3至2.3×1020原子/ cm3之间的二氧化硅介电层。一种包含ZTC电容器的集成电路，其包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅电介质层。形成包含Zinc电容器的集成电路的过程，该电容器包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅介电层。

74. 发明授权

US08164160B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08164160B2
公开(公告)日：2012-04-24
申请号：US12155232
申请日：2008-05-30
申请人： Yuichi Nakao , Takahisa Yamaha
发明人： Yuichi Nakao , Takahisa Yamaha
IPC分类号： H01L29/92
CPC分类号： H01L28/60 , H01L23/5223 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L27/0805 , H01L2224/05001 , H01L2224/05026 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05647 , H01L2224/13 , H01L2924/13091 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.
摘要翻译：根据本发明的半导体器件具有多层布线结构，其层叠并设置多个夹着绝缘膜的多层布线结构，并且包括：以铜为主要成分的铜线; 形成在铜线上的绝缘膜; 铝线，其以铝为主要成分，并形成在所述绝缘膜上，以通过形成为穿透所述绝缘膜的通孔与所述铜线电连接; 和形成在铝线上的表面保护膜; 并且所述表面保护膜形成有用于使铝线的一部分暴露于与外部部分电连接的电极焊盘的焊盘开口。

75. 发明申请

US20120091560A1 MIM Capacitors in Semiconductor Components 有权
标题翻译： MIM电容器在半导体组件
公开(公告)号：US20120091560A1
公开(公告)日：2012-04-19
申请号：US13334768
申请日：2011-12-22
申请人： Philipp Riess , Armin Fischer
发明人： Philipp Riess , Armin Fischer
IPC分类号： H01L29/92 , H01G4/018
CPC分类号： H01L23/5223 , H01L2924/0002 , Y10T29/43 , H01L2924/00
摘要： Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.
摘要翻译：公开了形成理想MIM电容器的结构和方法。单个电容器包括覆盖衬底的第一和第二金属结构，设置在第一金属结构的第一部分和第二金属结构的第一部分之间的第一介电材料。第二介电材料设置在第一金属结构的第二部分和第二金属结构的第二部分之间。在第一和第二金属结构的第二部分之间没有设置第一介电材料，并且在第一和第二金属结构的第一部分之间没有设置第二介电材料。第一和第二介电材料层包括具有相反的电容系数的材料。

76. 发明申请

US20120086105A1 SEMICONDUCTOR DEVICE HAVING CAPACITOR CAPABLE OF REDUCING ADDITIONAL PROCESSES AND ITS MANUFACTURE METHOD 有权
标题翻译：具有能够减少额外处理能力的电容器的半导体器件及其制造方法
公开(公告)号：US20120086105A1
公开(公告)日：2012-04-12
申请号：US13330630
申请日：2011-12-19
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L21/76802 , H01L21/76832 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.
摘要翻译：通过层间绝缘膜形成第一电容器凹部和布线沟槽。下部电极填充第一电容器凹部，并且第一布线填充布线沟槽。蚀刻停止膜和通孔层绝缘膜设置在层间绝缘膜上。第一通孔延伸穿过通孔层绝缘膜和蚀刻阻挡膜并到达第一布线，并且第一插头填充第一通孔。通过通孔层绝缘膜形成第二电容器凹部，第二电容器凹部至少部分地与下电极重叠，如图所示。上电极覆盖第二电容器凹部的底表面和侧表面。电容器由上电极，蚀刻停止膜和下电极构成。连接到第一插头的第二连接件形成在通孔层绝缘膜上。

77. 发明申请

US20120049257A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120049257A1
公开(公告)日：2012-03-01
申请号：US13208997
申请日：2011-08-12
申请人： SungHo Lee , Jin Choi , Yong-Ho Yoo , Jong-Hyuk Kang , Hyun-Joo Cha , Tae-Jung Park
发明人： SungHo Lee , Jin Choi , Yong-Ho Yoo , Jong-Hyuk Kang , Hyun-Joo Cha , Tae-Jung Park
IPC分类号： H01L27/108 , H01L29/92
CPC分类号： H01L27/10814 , H01L27/10852 , H01L28/90
摘要： A DRAM device can include a plurality of capacitors that are arranged in a line in a first direction. Each of the capacitors can include an upper electrode. A contact pattern having a line shape can extend in the first direction and can be electrically connected to each of the upper electrodes. A conductor can be on the contact pattern opposite the upper electrodes and can be electrically connected to the contact pattern.
摘要翻译： DRAM装置可以包括沿第一方向排列成一行的多个电容器。每个电容器可以包括上电极。具有线状的接触图案可以在第一方向上延伸并且可以电连接到每个上电极。导体可以在与上电极相对的接触图案上，并且可以电连接到接触图案。

78. 发明申请

US20120032302A1 VERTICAL CAPACITORS FORMED ON SEMICONDUCTING SUBSTRATES 有权
标题翻译：形成半导体衬底的垂直电容
公开(公告)号：US20120032302A1
公开(公告)日：2012-02-09
申请号：US12850400
申请日：2010-08-04
申请人： David M. Smith
发明人： David M. Smith
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01G4/012 , H01G4/306 , H01L28/86 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： Semiconductor devices (100) and methods of making the same. Each of the semiconductor devices includes a substrate (102) having a first surface (118) and an opposing second surface. A vertical capacitive element (104) is disposed on the first surface of the substrate. The vertical capacitive element comprises a plurality of parallel conductive plates (120b, 120d, 120f, 120h, 120j, 120l, 120n) extending transverse to the first surface of the substrate. Adjacent conductive plates are spaced a distance D from each other. A dielectric material (104) can be disposed in a space separating the adjacent conductive plates. Each of the conductive plates has a height-to-width (h/w) ratio greater than or equal to one.
摘要翻译：半导体器件（100）及其制造方法。每个半导体器件包括具有第一表面（118）和相对的第二表面的衬底（102）。垂直电容元件（104）设置在基板的第一表面上。垂直电容元件包括横向于衬底的第一表面延伸的多个平行导电板（120b，120d，120f，120h，120j，120l，120n）。相邻的导电板彼此间隔开距离D. 电介质材料（104）可以设置在分隔相邻的导电板的空间中。每个导电板的高度 - 宽度（h / w）比大于或等于1。

79. 发明申请

US20120018843A1 Scalable Integrated Circuit High Density Capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US20120018843A1
公开(公告)日：2012-01-26
申请号：US13162257
申请日：2011-06-16
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Rangnathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Rangnathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

80. 发明申请

US20120001298A1 Method for manufacturing thin film capacitor and thin film capacitor obtained by the same 有权
标题翻译：制造薄膜电容器和薄膜电容器的方法
公开(公告)号：US20120001298A1
公开(公告)日：2012-01-05
申请号：US13067800
申请日：2011-06-28
申请人： Hideaki Sakurai , Toshiaki Watanabe , Nobuyuki Soyama , Guillaume Guegan
发明人： Hideaki Sakurai , Toshiaki Watanabe , Nobuyuki Soyama , Guillaume Guegan
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/60 , B82Y30/00 , C04B35/4682 , C04B2235/3213 , C04B2235/441 , C04B2235/781 , C04B2235/785 , C04B2235/787 , H01G4/01 , H01G4/1227 , H01G4/33 , H01L21/02197 , H01L21/02282 , H01L28/55 , H01L28/65
摘要： A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.
摘要翻译：薄膜电容器的特征在于形成下电极，在不施加温度大于300℃的退火工艺的情况下将组合物涂覆在下电极上，在从环境温度至500℃的范围内的预定温度下干燥并在500〜800℃的范围内的预定温度下煅烧并高于干燥温度。从涂覆到煅烧的过程进行从涂覆到煅烧一次或至少两次的过程，或者从涂覆到干燥的过程进行至少两次，然后进行一次煅烧。在第一次煅烧后形成的电介质薄膜的厚度为20〜600nm。初始煅烧步骤后形成的下部电极的厚度与电介质薄膜的厚度之比（下部电极的厚度/电介质薄膜的厚度）优选在0.10〜15.0的范围内。

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