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71. 发明授权

US11249907B1 Write-back cache policy to limit data transfer time to a memory device 有权
公开(公告)号：US11249907B1
公开(公告)日：2022-02-15
申请号：US17114613
申请日：2020-12-08
申请人： Micron Technology, Inc.
发明人： Tony M. Brewer
IPC分类号： G06F12/0802
摘要： Systems, apparatuses, and methods related to a write-back cache policy to limit data transfer time to a memory device are described. A controller can orchestrate performance of operations to write data to a cache according to a write-back policy and write addresses associated with the data to a buffer. The controller can further orchestrate performance of operations to limit an amount of data stored by the buffer and/or a quantity of addresses stored in the buffer. In response to a power failure, the controller can cause the data stored in the cache to be flushed to a persistent memory device in communication with the cache.

72. 发明授权

US11243877B2 Method, apparatus for data management, and non-transitory computer-readable storage medium for storing program 有权
公开(公告)号：US11243877B2
公开(公告)日：2022-02-08
申请号：US16378848
申请日：2019-04-09
申请人： FUJITSU LIMITED
发明人： Shun Gokita
IPC分类号： G06F12/02 , G06F12/08 , G06F3/06 , G06F13/00 , G06F12/0802
摘要： A method for data management by a computer coupled to a solid state drive (SSD), the SSD being configured to include blocks and channels, each of the blocks being a first area as a unit of data deletion and being configured to include pages, each of the pages being a second area as a unit of data access in the SSD, each of the channels being a transmission and reception route of data to and from the block, the method includes: executing allocation processing for allocating, to a management target having a fixed length determined, a logical block including the blocks coupled to different channels, executing management processing for, when a size of a division management target is more than a size of the page, allocating the division management target to the pages coupled to the different channels included in the logical block allocated to the management target.

73. 发明申请

US20220027288A1 TECHNOLOGIES FOR LOW-LATENCY CRYPTOGRAPHY FOR PROCESSOR-ACCELERATOR COMMUNICATION 有权
公开(公告)号：US20220027288A1
公开(公告)日：2022-01-27
申请号：US17496147
申请日：2021-10-07
申请人： Intel Corporation
发明人： SANTOSH GHOSH , LUIS S. KIDA , RESHMA LAL
IPC分类号： G06F12/14 , H04L9/32 , G06F21/76 , G06F21/60 , H04L9/08 , G06F9/455 , G06F21/57 , G06F21/64 , H04L12/24 , G06F21/79 , H04L9/06 , G06F9/38 , G06F12/0802
摘要： Technologies for secure data transfer include a computing device having a processor, an accelerator, and a security engine, such as a direct memory access (DMA) engine or a memory-mapped I/O (MMIO) engine. The computing device initializes the security engine with an initialization vector and a secret key. During initialization, the security engine pre-fills block cipher pipelines and pre-computes hash subkeys. After initialization, the processor initiates a data transfer, such as a DMA transaction or an MMIO request, between the processor and the accelerator. The security engine performs an authenticated cryptographic operation for the data transfer operation. The authenticated cryptographic operation may be AES-GCM authenticated encryption or authenticated decryption. The security engine may perform encryption or decryption using multiple block cipher pipelines. The security engine may calculate an authentication tag using multiple Galois field multipliers. Other embodiments are described and claimed.

74. 发明申请

US20220027267A1 USING MULTI-TIERED CACHE TO SATISFY INPUT/OUTPUT REQUESTS 有权
公开(公告)号：US20220027267A1
公开(公告)日：2022-01-27
申请号：US17494680
申请日：2021-10-05
申请人： International Business Machines Corporation
发明人： Lokesh Mohan Gupta , Edward Hsiu-Wei Lin , Beth Ann Peterson , Matthew G. Borlick
IPC分类号： G06F12/0802 , G06F3/06
摘要： A computer-implemented method, according to one approach, includes: determining whether to satisfy an I/O request using a first tier of memory in a secondary cache by inspecting a bypass indication in response to determining that the input/output (I/O) request includes a bypass indication. The secondary cache is coupled to a primary cache and a data storage device. The secondary cache also includes the first tier of memory and a second tier of memory. Moreover, in response to determining to satisfy the I/O request using the first tier of memory in the secondary cache, the I/O request is satisfied using the first tier of memory in the secondary cache. The updated data is also destaged from the secondary cache to the data storage device in response to determining that data associated with the I/O request has been updated as the result of satisfying the I/O request using the secondary cache.

75. 发明授权

US11231852B2 Efficient sharing of non-volatile memory 有权
公开(公告)号：US11231852B2
公开(公告)日：2022-01-25
申请号：US15845723
申请日：2017-12-18
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： Anirudh Badam , Sriram Govindan , Bikash Sharma , Badriddine Khessib , Iyswarya Narayanan , Aishwarya Ganesan
IPC分类号： G06F3/06 , G06F12/0802 , G06F9/50
摘要： In the embodiment a determination is made, for one or more applications being executed by the computing system, of an amount of the first or second memory being used by the one or more applications. Based on the determination, a portion of the memory resources of the third memory are configured to function with the first or second memory when it is determined that the amount of the first or second memory being used by the one or more applications is not sufficient for the memory needs of the one or more applications and a portion of the memory resources of the third memory are removed from functioning with the first or second memory when it is determined that the amount of the first or second memory being used by the one or more applications is more than is needed for the memory needs of the one or more applications.

76. 发明授权

US11226741B2 I/O behavior prediction based on long-term pattern recognition 有权
公开(公告)号：US11226741B2
公开(公告)日：2022-01-18
申请号：US16175947
申请日：2018-10-31
申请人： EMC IP Holding Company LLC
发明人： Owen Martin , Malak Alshawabkeh
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0802 , G06N3/08
摘要： Described herein is a system, and related techniques, for predicting I/O requests that are not necessarily directed to sequential sectors of a physical storage device. In some embodiments, I/O patterns that do not involve sequential-sector access, and that may be relatively long-term patterns, may be recognized. To recognize such patterns, deep machine-learning techniques may be used, for example, using neural networks. Such neural networks may be a recurrent neural network such as, for example, an LSTM-RNN. I/O streams for a workstream may be sampled for specific I/O features to produce a time series of I/O feature values of a workstream, and this time series of data may be fed to a prediction engine, e.g., an LSTM-RNN to predict one or more future I/O features values, and I/O actions may be taken based on these predicted feature values.

77. 发明申请

US20220013179A1 NOISE REDUCTION DURING PARALLEL PLANE ACCESS IN A MULTI-PLANE MEMORY DEVICE 有权
公开(公告)号：US20220013179A1
公开(公告)日：2022-01-13
申请号：US16946867
申请日：2020-07-09
申请人： Micron Technology, Inc.
发明人： Theodore Pekny
IPC分类号： G11C16/26 , G11C16/04 , G06F12/0802
摘要： A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to track a status of the plurality of independent plane driver circuits and detect an occurrence of a quiet event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a high noise event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the high noise event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to determine whether the first independent plane driver circuit has a higher priority than the second independent plane driver circuit. Responsive to determining that the first independent plane driver circuit has a higher priority than the second independent plane driver circuit, the control logic is to suspend the high noise event associated with the second independent plane driver circuit and permitting the quiet event associated with the first independent plane driver circuit to occur.

78. 发明授权

US11210429B2 Memory access gate 有权
公开(公告)号：US11210429B2
公开(公告)日：2021-12-28
申请号：US16814013
申请日：2020-03-10
申请人： Micron Technology, Inc.
发明人： Giuseppe Cariello
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F21/74 , G06F12/0802 , G06F12/14 , G06F21/30
摘要： Methods, systems, and devices for a memory access gate are described. A memory device may include a controller, memory dice, and a pad for receiving an externally provided control signal, such as a chip enable signal. The memory device may include a switching component for selecting the externally provided control signal or an internally generated control signal. The controller may provide the selected control signal to a memory die. The memory device may determine whether it is operating in a first mode or a second mode, and select the externally provided control signal or the internally generated control signal based on the determination. The first mode may be a diagnostic mode in some cases. The controller may include a secure register whose value may impact or control the switching. An authenticated host device may direct the controller to write the value to the secure register.

79. 发明申请

US20210398949A1 MEMORY DEVICE INCLUDING MODULAR MEMORY UNITS AND MODULAR CIRCUIT UNITS FOR CONCURRENT MEMORY OPERATIONS 有权
公开(公告)号：US20210398949A1
公开(公告)日：2021-12-23
申请号：US17467011
申请日：2021-09-03
申请人： Sunrise Memory Corporation
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , H01L25/00 , G06N3/02 , G06F3/06 , G06F11/10 , G06F12/0802
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

80. 发明授权

US11204801B2 Method and apparatus for scheduling thread order to improve cache efficiency 有权
公开(公告)号：US11204801B2
公开(公告)日：2021-12-21
申请号：US16684077
申请日：2019-11-14
申请人： Intel Corporation
发明人： Justin DeCell , Saurabh Sharma
IPC分类号： G06F9/48 , G06F9/52 , G06T15/80 , G06F12/0802 , G06F9/38 , G06F9/30 , G06F9/50 , G06T15/00
摘要： Systems and methods for scheduling thread order to improve cache efficiency are disclosed. In one embodiment, a graphics processor includes processing resources and schedule and dispatch logic to schedule and dispatch threads to the processing resources. The schedule and dispatch logic is configured to receive threads, to schedule and dispatch the threads based on a forward thread dispatch having a forward thread order, and to determine whether to disable a reversing of a thread order upon completion of at least a portion of the forward thread dispatch including a completion or ending of a draw call or a dispatch.

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