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71. 发明申请

US20220293678A1 MAGNETIC MEMORY 有权
公开(公告)号：US20220293678A1
公开(公告)日：2022-09-15
申请号：US17410806
申请日：2021-08-24
申请人： KIOXIA CORPORATION
发明人： Yoshihiro UEDA , Naoharu Shimomura , Tsuyoshi Kondo
IPC分类号： H01L27/22 , H01L43/02 , H01L43/08 , G11C11/16
摘要： A magnetic memory includes a planar electrode and a first wiring spaced from the electrode. A first magnetic member is between the electrode and the first wiring. The first magnetic member has a first end facing the first wiring and a second end facing the electrode. A magnetoresistive element is connected to the first end. A transistor is between the magnetoresistive element and the first wiring. The transistor has a channel layer and a gate electrode covering at least part of an outer periphery of the channel layer. One end of the channel layer is connected to the magnetoresistive element, and another end of the channel layer is connected to the first wiring. A second wiring has a portion between the electrode and the second end of the first magnetic member. A control circuit is electrically connected to the gate electrode, the electrode, and the first and second wirings.

72. 发明申请

US20220293177A1 RESISTIVE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
公开(公告)号：US20220293177A1
公开(公告)日：2022-09-15
申请号：US17827846
申请日：2022-05-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： MOONKI JUNG
IPC分类号： G11C13/00 , G11C11/16 , H01L23/00 , H01L25/065 , H01L25/18
摘要： A method of programming a resistive memory device, and a corresponding resistive memory device, which includes the resistive memory device, in response to a write command, applying a write pulse to a selected memory cell arranged in a region where a selected word line intersects with a selected bit line; and after the applying the write pulse, applying a dummy pulse to at least one unselected memory cell. The at least one unselected memory cell is connected to at least one of the selected word line, the selected bit line, a first word line adjacent to the selected word line, and a first bit line adjacent to the selected bit line.

73. 发明申请

US20220285610A1 MULTI-BIT MEMORY CELL, ANALOG-TO-DIGITAL CONVERTER, DEVICE AND METHOD 有权
公开(公告)号：US20220285610A1
公开(公告)日：2022-09-08
申请号：US17508819
申请日：2021-10-22
申请人： BEIHANG UNIVERSITY
发明人： Weisheng ZHAO , Zhaohao WANG , Kaihua CAO , Gefei WANG , Min WANG
IPC分类号： H01L43/06 , G11C11/16 , H01L27/22 , H01L43/04
摘要： The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

74. 发明申请

US20220277782A1 READ CIRCUIT FOR MAGNETIC TUNNEL JUNCTION (MTJ) MEMORY 有权
公开(公告)号：US20220277782A1
公开(公告)日：2022-09-01
申请号：US17748560
申请日：2022-05-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Gaurav Gupta , Zhiqiang Wu
IPC分类号： G11C11/16 , H01L27/22 , H01L43/02
摘要： In some embodiments, the present application provides a memory device. The memory device includes a memory cell array comprising a plurality of magnetic tunnel junction (MTJ) memory cells arranged in columns and rows, a read bias circuit connected to the memory cell array and configured to provide a reading bias for a MTJ memory cell of the memory cell array, and a first non-linear resistance device connected in series and between the MTJ memory cell and the read bias circuit. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

75. 发明申请

US20220276807A1 MRAM ACCESS COORDINATION SYSTEMS AND METHODS 有权
公开(公告)号：US20220276807A1
公开(公告)日：2022-09-01
申请号：US17745839
申请日：2022-05-16
申请人： Integrated Silicon Solution, (Cayman) Inc.
发明人： Benjamin LOUIE , Neal BERGER , Lester CRUDELE
IPC分类号： G06F3/06 , G11C11/16 , G11C29/00
摘要： Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

76. 发明授权

US11430499B2 Reducing read disturbance error in tag array 有权
公开(公告)号：US11430499B2
公开(公告)日：2022-08-30
申请号：US17204957
申请日：2021-03-18
申请人： Hossein Asadi , Elham Cheshmikhanikhanghah
发明人： Hossein Asadi , Elham Cheshmikhanikhanghah
IPC分类号： G11C11/00 , G11C11/16 , H03K19/20
摘要： A circuit for reducing read disturbance error in a tag array. The circuit includes a decoder, a plurality of m-bit comparators, and a plurality of n-bit comparators. The decoder is configured to enable access to a respective set of the tag array based on a value of an index of a requested address. Each respective m-bit comparator is configured to enable access to a respective plurality of Most Significant Bits (MSBs) of the respective set responsive to each respective Least Significant Bit (LSB) of a respective plurality of LSBs of the respective set being equal to a respective LSB of a tag of the requested address. Each respective n-bit comparator is configured to enable access to the respective set by a data bus responsive to each respective MSB of the respective plurality of MSBs being equal to a respective MSB of the tag.

77. 发明申请

US20220270675A1 APPARATUS AND METHOD FOR CONTROLLING GRADUAL CONDUCTANCE CHANGE IN SYNAPTIC ELEMENT 有权
公开(公告)号：US20220270675A1
公开(公告)日：2022-08-25
申请号：US17628280
申请日：2020-07-30
申请人： Jun-sung KIM
发明人： Jun-sung KIM
IPC分类号： G11C11/54 , G11C11/16 , G11C13/00 , G06N3/08 , G06N3/063
摘要： The present invention provides a memory apparatus capable of causing a gradual resistance change for information processing in an analog manner to a synaptic element for implementing a neuromorphic system. To this end, the present invention provides a memory apparatus including: a memory array including a plurality of memory cells capable of selectively storing logic states and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a writing step and a reading step; a writing unit; and a reading unit, wherein the controller selects, in the writing step, one or more memory cells from among the plurality of memory cells through the writing unit, sequentially applies a writing voltage thereto to allow the logic states to be written therein, and applies, in the reading step, a reading voltage to the one or more memory cells, which are selected to have the logic states written therein, through the reading unit so as to determine synaptic weights through a sum of currents flowing through the one or more memory cells so that the selected one or more memory cells are allowed to be recognized to operate as one synaptic element.
The present invention also provides a method for determining a synaptic weight in a memory apparatus including a memory array including a plurality of memory cells capable of selectively storing logic states, bit lines and word lines connected to the plurality of memory cells, the method including: (a) selecting one or more memory cells from among the plurality of memory cells, and sequentially applying a writing voltage to write logic states therein; (b) applying a reading voltage to the one or more memory cells that has been selected to have the logic states written therein; and (c) determining, by the applied reading voltage, a synaptic weight through a sum of currents flowing through the one or more memory cells that has been selected to have the logic states written therein, wherein the selected one or more memory cells are recognized to operate as one synaptic element.

78. 发明申请

US20220270658A1 Device for Data Storage and Processing, and Method Thereof 有权
公开(公告)号：US20220270658A1
公开(公告)日：2022-08-25
申请号：US17631156
申请日：2020-06-23
申请人： Politecnico di Torino , Universita Degli Studi Di Roma Tor Vergata
发明人： Fabrizio Riente , Marco Ottavi , Marco Vacca , Giovanna Turvani
IPC分类号： G11C11/16 , H03K19/20 , G11C19/08
摘要： A device for data storage and processing includes: at least two input racetrack elements having a plurality of first magnetization regions; at least one output racetrack element having a plurality of second magnetization regions, wherein a magnetization vector is adapted to switch from a first direction to the opposite one, or vice versa, by way of a magnetic field of reduced intensity compared with a magnetic field required to produce a similar switching of a magnetization vector of the first magnetization region, wherein the input racetrack elements and output racetrack element are configured in such a way as to constitute at least one elementary logic gate, wherein at least two of the first magnetization regions are magnetically coupled to at least one of the second magnetization regions.

79. 发明申请

US20220262857A1 METHOD AND RELATED APPARATUS FOR IMPROVING MEMORY CELL PERFORMANCE IN SEMICONDUCTOR-ON-INSULATOR TECHNOLOGY 有权
公开(公告)号：US20220262857A1
公开(公告)日：2022-08-18
申请号：US17734315
申请日：2022-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jack Liu , Charles Chew-Yuen Young
IPC分类号： H01L27/22 , H01L43/02 , G11C11/16
摘要： In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.

80. 发明申请

US20220261625A1 PROCESSING DEVICE BASED ON MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT AND ELECTRONIC SYSTEM INCLUDING THE PROCESSING DEVICE 有权
公开(公告)号：US20220261625A1
公开(公告)日：2022-08-18
申请号：US17474466
申请日：2021-09-14
申请人： Samsung Electronics Co., Ltd.
发明人： Kangho LEE , Boyoung SEO , Sangjoon KIM , Seungchul JUNG
IPC分类号： G06N3/063 , G11C11/16
摘要： Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

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