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71. 发明授权

US5396089A Method of generating active semiconductor structures by means of starting structures which have a 2D charge carrier layer parallel to the surface 失效
标题翻译：通过具有平行于表面的2D电荷载体层的起始结构产生有源半导体结构的方法
公开(公告)号：US5396089A
公开(公告)日：1995-03-07
申请号：US34315
申请日：1993-03-22
申请人： Andreas D. Wieck , Klaus Ploog
发明人： Andreas D. Wieck , Klaus Ploog
IPC分类号： H01L21/265 , H01L21/28 , H01L21/335 , H01L29/06 , H01L29/32 , H01L29/423 , H01L29/51 , H01L29/775 , H01L29/86 , H01L29/20 , H01L29/78 , H01L29/161 , H01L29/205
CPC分类号： H01L21/2654 , B82Y10/00 , H01L21/28158 , H01L29/0653 , H01L29/32 , H01L29/4238 , H01L29/51 , H01L29/513 , H01L29/66469 , H01L29/775 , H01L29/86
摘要： A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another. The source and drain are only connected by a narrow channel 44 the width of which is continuously tunable by a gate potential which is simultaneously applied to the two gate regions relative to the source, so that a pronounced change of the carrier concentration and thus of the channel resistance arises. The specification also describes integrated circuits made using the same methods.
摘要翻译：提出了具有FET的所有特性的准一维载流子通道的单极电子元件。该部件可以非常简单地制造，具有“自对准”和具有低容量的线性门来代替平面栅极。以这种方式，组件的非常高的工作频率是可能的。该结构包括通过例如GaAs的外延形成的具有高载流子迁移率的初始均匀的2D层。聚焦离子（例如Ga +与100keV）的注入会局部地破坏电子层的导电性。即使在用带隙辐射照射碎片之后，照射区域在低温或室温下保持绝缘。绝缘层的写入沿着芯片上的两条路径进行，使得2D载体层被细分成彼此绝缘的三个区域。源极和漏极仅由窄通道44连接，窄通道44的宽度可通过栅极电位连续可调，该栅极电位同时施加到相对于源极的两个栅极区域，使得载流子浓度明显变化通道电阻出现。本说明书还描述了使用相同方法制造的集成电路。

72. 发明授权

US5348773A Threshold switching device 失效
公开(公告)号：US5348773A
公开(公告)日：1994-09-20
申请号：US82112
申请日：1993-06-28
申请人： Keith W. Michael , Udo C. Pernisz
发明人： Keith W. Michael , Udo C. Pernisz
IPC分类号： H01L29/86 , G06N3/063 , H01L45/00 , H01L49/02 , B05D3/06 , B05D3/02 , B05D5/12
CPC分类号： H01L45/1608 , G06N3/063 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/145 , Y10T428/265 , Y10T428/31678
摘要： This invention relates to a method of forming a threshold switching device which exhibits negative differential resistance and to the devices formed thereby. The method comprises depositing a silicon dioxide film derived from hydrogen silsesquioxane resin between at least two electrodes and then applying a voltage above a threshold voltage across the electrodes.

73. 发明授权

US5293335A Ceramic thin film memory device 失效
标题翻译：陶瓷薄膜记忆装置
公开(公告)号：US5293335A
公开(公告)日：1994-03-08
申请号：US988046
申请日：1992-12-09
申请人： Udo C. Pernisz , Keith W. Michael , Loren A. Haluska
发明人： Udo C. Pernisz , Keith W. Michael , Loren A. Haluska
IPC分类号： H01L29/86 , G06N3/063 , H01L45/00 , H01L49/02 , G11C11/56
CPC分类号： H01L45/1608 , G06N3/063 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/145 , Y10T428/265 , Y10T428/31678
摘要： A digital memory circuit for electronic applications. The circuit has at least one memory element connected in series with a load resistor. The digital memory circuit also includes a voltage supply and a data output terminal. The memory element in the digital memory circuit is in the form of a silicon dioxide film derived from a hydrogen silsesquioxane resin. The silicon dioxide film is characterized by a jV curve which includes both resistive and conductive regions for the memory element.
摘要翻译：一种用于电子应用的数字存储电路。电路具有与负载电阻串联连接的至少一个存储元件。数字存储电路还包括电压源和数据输出端。数字存储电路中的存储元件是由氢倍半硅氧烷树脂衍生的二氧化硅膜的形式。二氧化硅膜的特征在于包括存储元件的电阻和导电区域的jV曲线。

74. 发明授权

US4985737A Solid state quantum mechanical electron and hole wave devices 失效
标题翻译：固态量子力学电子和空穴波器件
公开(公告)号：US4985737A
公开(公告)日：1991-01-15
申请号：US272175
申请日：1988-11-16
申请人： Thomas K. Gaylord , Kevin F. Brennan , Elias N. Glytsis
发明人： Thomas K. Gaylord , Kevin F. Brennan , Elias N. Glytsis
IPC分类号： H01L29/12 , H01L29/15 , H01L29/86
CPC分类号： B82Y10/00 , H01L29/122 , H01L29/152 , H01L29/155 , H01L29/86 , Y10S977/759 , Y10S977/761
摘要： Solid state quantum mechanical electron or hole wave devices which are analogous to optical thin-film devices provide, among other things, energy selectivity for substantially ballistic electron or hole wave propagation in superlattice structures at energies above the superlattice potential energy barriers. Further, in accordance with the inventive method, the inventive devices may be designed by transforming existing optical thin-film design methods and existing optical interference filter designs into inventive semiconductor devices. This transformation from existing optical design methods and existing optical interference filter designs into semiconductor devices is performed for electron devices by mapping the optical phase index of refraction into a first solid state index of refraction for phase quantities which is proportional to the square root of the product of the electron kinetic energy and the electron effective mass and by mapping the optical amplitude index of refraction into a second solid state index of refraction for amplitude quantities which is proportional to the square root of the electron kinetic energy divided by the electron effective mass.
摘要翻译：类似于光学薄膜器件的固态量子力学电子或空穴波器件尤其提供了在超晶格势垒能量以上的能量下在超晶格结构中的基本弹道电子或空穴波传播的能量选择性。此外，根据本发明的方法，可以通过将现有的光学薄膜设计方法和现有的光学干涉滤光器设计转变为本发明的半导体器件来设计本发明的器件。对于电子器件，通过将光学相位折射率映射到与产品的平方根成比例的相位量的第一固态折射率来对现有的光学设计方法和现有的光学干涉滤光器设计进行半导体器件的转换的电子动能和电子有效质量，并且通过将光学振幅折射率映射到与电子动能的平方根除以电子有效质量成比例的幅度量的第二固体折射率折射率。

75. 发明授权

US4851886A Binary superlattice tunneling device and method 失效
标题翻译：二元超晶格隧道装置及方法
公开(公告)号：US4851886A
公开(公告)日：1989-07-25
申请号：US872795
申请日：1986-06-11
申请人： Jhang W. Lee , Mark A. Reed
发明人： Jhang W. Lee , Mark A. Reed
IPC分类号： H01L47/00 , H01L29/06 , H01L29/15 , H01L29/201 , H01L29/66 , H01L29/86 , H01L29/88
CPC分类号： B82Y10/00 , H01L29/155 , H01L29/882
摘要： A resonant tunneling diode (30) with anode (40) and cathode (32) separated by binary short-period superlattice tunneling barriers (34,38) with a quantum well (36) between is disclosed. Enhancement and depletion mode diodes are disclosed.
摘要翻译：公开了具有阳极（40）和阴极（32）的谐振隧道二极管（30），其间隔二极短周期超晶格隧穿势垒（34,38）与量子阱（36）之间。公开了增强和耗尽型二极管。

76. 发明授权

US4649405A Electron ballistic injection and extraction for very high efficiency, high frequency transferred electron devices 失效
标题翻译：电子弹道注射和提取用于非常高效率的高频转移电子器件
公开(公告)号：US4649405A
公开(公告)日：1987-03-10
申请号：US598755
申请日：1984-04-10
申请人： Lester F. Eastman
发明人： Lester F. Eastman
IPC分类号： H01L29/36 , H01L29/864 , H01L47/02 , H01L29/88 , H01L29/20 , H01L29/86
CPC分类号： H01L47/026 , H01L29/365 , H01L29/864
摘要： A high frequency transferred electron device having electron ballistic injection and extraction for very high efficiency is disclosed. The device comprises a semiconductor body having at least two electrodes with a thin barrier layer being formed at one electrode for launching ballistic electrons at a controlled kinetic energy into the body. The body includes a drift region having a low, controlled density of electrons and impurities. A second heavily doped (N+) collector semiconductor layer at the second electrode insures that there is no barrier at the second electrode interface, thereby allowing energetic electrons to be removed from the drift region and allowing entry of new ballistic electrons to improve the efficiency and frequency response of the device.
摘要翻译：公开了具有非常高效率的电子弹注射和提取的高频转移电子器件。该装置包括具有至少两个电极的半导体本体，该电极具有薄的阻挡层，该电极在一个电极处形成，用于以受控的动能向身体发射弹道电子。身体包括具有低的受控密度的电子和杂质的漂移区域。在第二电极处的第二重掺杂（N +）集电极半导体层确保在第二电极界面处不存在阻挡层，从而允许从漂移区域去除高能电子，并允许新的弹道电子进入以提高效率和频率设备响应。

77. 发明授权

US4646115A Semiconductor devices having field-relief regions 失效
标题翻译：具有场释放区域的半导体器件
公开(公告)号：US4646115A
公开(公告)日：1987-02-24
申请号：US859852
申请日：1986-05-01
申请人： John M. Shannon , John A. G. Slatter , David J. Coe
发明人： John M. Shannon , John A. G. Slatter , David J. Coe
IPC分类号： H01L29/06 , H01L29/40 , H01L29/47 , H01L29/78 , H01L29/86 , H01L29/861 , H01L29/872 , H01L29/80
CPC分类号： H01L29/402 , H01L29/0619 , H01L29/407 , H01L29/408 , H01L29/7813 , H01L29/8618 , H01L29/872
摘要： Separate areas of an active unipolar barrier, e.g. a Schottky barrier, of a semiconductor device are located between closely-spaced field-relief regions which provide the device with an improved voltage blocking characteristic. The flow of minority carriers into the adjacent body portion under forward bias is restricted by providing, at least at the areas of the field-relief regions, a layer of different material from that of the body portion and from that of the unipolar barrier-forming means. The layer of different material may form a high-impedance electrical connection with the field-relief regions, and/or it may form with the body portion a heterojunction such as, for example, a Schottky barrier of higher barrier height, a barrier between different band gap materials or a MIS structure, which heterojunction forms part of the field-relief regions.
摘要翻译：活性单极屏障的单独区域，例如半导体器件的肖特基势垒位于紧密间隔的磁场释放区域之间，为该器件提供改进的电压阻挡特性。少数载体在正向偏压下进入相邻主体部分的流动受到限制，至少在场浮雕区域的区域处设置与主体部分不同的材料层和单极屏障形成层手段。不同材料的层可以形成与场致发射区域的高阻抗电连接，和/或其可以与主体部分形成异质结，例如具有较高势垒高度的肖特基势垒，不同的屏障之间的屏障带隙材料或MIS结构，其中异质结形成了场平面区域的一部分。

78. 发明授权

US4467344A Bidirectional switch using two gated diode switches in a single dielectrically isolated tub 失效
标题翻译：双向开关在单个介质隔离的桶中使用两个门控二极管开关
公开(公告)号：US4467344A
公开(公告)日：1984-08-21
申请号：US333700
申请日：1981-12-23
申请人： Gee-Kung Chang , Adrian R. Hartman , Harry T. Weston
发明人： Gee-Kung Chang , Adrian R. Hartman , Harry T. Weston
IPC分类号： H01L29/86 , H01L21/762 , H01L21/764 , H01L27/08 , H01L29/739 , H01L29/747 , H01L29/06 , H01L29/74
CPC分类号： H01L29/7392 , H01L21/76297 , H01L21/764 , H01L27/0814
摘要： A semiconductor structure contains two interconnected gated diode switches in a common dielectrically isolated semiconductor tub. This structure functions as a bidirectional switch. A gate region physically located between the two switches provides electrical isolation to allow proper operation.
摘要翻译：半导体结构在公共介电隔离的半导体衬底中包含两个互连的门控二极管开关。该结构用作双向开关。物理上位于两个开关之间的栅极区域提供电隔离以允许正确的操作。

79. 发明授权

US4247863A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4247863A
公开(公告)日：1981-01-27
申请号：US937937
申请日：1978-08-30
申请人： Ryoiku Togei
发明人： Ryoiku Togei
IPC分类号： G11C11/35 , H01L27/10 , H01L27/108 , H01L29/86 , H01L27/12
CPC分类号： G11C11/35 , H01L27/10 , H01L27/108
摘要： Disclosed herein is a small-sized semiconductor memory device, wherein an N.sup.+ (P.sup.+)-type single region having an input function and an output function and an electrode for controlling the electrical potential in a P(N)-type Si substrate are provided on the top surface of the P(N)-type Si substrate. In order to store carriers, i.e., an information, in the bulk of the substrate, an N (P)-type buried layer is formed below the N.sup.+ (P.sup.+)-type input-output region, mentioned above. Information is quickly transferred from or into the buried layer by means of the punch-through effect, which is realized by spreading a depletion layer formed at a PN junction between the input-output region and the Si substrate. Since the carriers are stored in the bulk of the substrate, the size of the memory device is reduced and the surface property of the device does not exert a harmful influence on the carriers.
摘要翻译：这里公开了一种小型半导体存储器件，其中具有输入功能和输出功能的N +（P +）型单区域和用于控制P（N）型Si衬底中的电位的电极设置在 P（N）型Si衬底的顶表面。为了在载体的大部分中存储载流子即信息，在上述N +（P +）型输入输出区域的下方形成N（P）型掩埋层。通过穿透效应将信息快速地传送到掩埋层中，通过扩展在输入 - 输出区域和Si衬底之间的PN结处形成的耗尽层来实现。由于载体存储在基板的主体中，所以存储器件的尺寸减小，并且器件的表面特性不会对载体产生有害的影响。

80. 发明授权

US3945028A High speed, high power plasma thyristor circuit 失效
标题翻译：高速，高功率等离子体晶闸管电路
公开(公告)号：US3945028A
公开(公告)日：1976-03-16
申请号：US354580
申请日：1973-04-26
申请人： Surinder Krishna , Chang Kwei Chu
发明人： Surinder Krishna , Chang Kwei Chu
IPC分类号： H01L29/86 , G01S7/282 , H01L29/74 , H01L29/861 , H01L29/866 , H01L29/90
CPC分类号： H01L29/861 , G01S7/282
摘要： A plasma thyristor circuit is provided for generating high power, ultra-short duration electrical signals. A silicon semiconductor body has first, second and third impurity regions therein with a PN junction formed at the transition between the first and second or the second and third impurity regions. The second impurity region has an impurity concentration of less than about 5 .times. 10.sup.14 atoms/cm.sup.3, and a width of greater than about 80 microns. The ratio of the punch-through voltage of the second impurity region to the reverse breakdown voltage of the PN junction is between 0.3 and 0.7. Power sources apply both a reverse bias voltage across the body greater than said punch-through voltage and less than said reverse breakdown voltage, and a current to the body having a density greater than the saturation current density of the second impurity region.
摘要翻译：提供等离子体晶闸管电路用于产生大功率，超短时间的电信号。硅半导体本体具有其中在第一和第二或第二和第三杂质区之间的过渡处形成PN结的第一，第二和第三杂质区。第二杂质区的杂质浓度小于约5×10 14原子/ cm 3，宽度大于约80微米。第二杂质区的穿通电压与PN结的反向击穿电压的比值在0.3和0.7之间。电源同时施加超过所述穿通电压并小于所述反向击穿电压的反向偏置电压，以及具有大于第二杂质区域的饱和电流密度的密度的电流。

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