专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US08547548B1 Final defect inspection system 有权
标题翻译：最终缺陷检查系统
公开(公告)号：US08547548B1
公开(公告)日：2013-10-01
申请号：US13721019
申请日：2012-12-20
申请人： Kinsus Interconnect Technology Corp.
发明人： Chia-Chi Lo , Cheng-Hsiung Yang Yang , Jun-Chung Hsu
IPC分类号： G01N21/00
CPC分类号： G01N21/8803 , G01N2021/8861 , G01N2021/888
摘要： Disclosed is a final defect inspection system, which including a host device, a microscope, a bar code scanner, a support tool, a signal transceiver and an electromagnetic pen. The bar code scanner scans a bar code on a circuit board provided on the support plate. The host device selects data and a circuit layout diagram from the database corresponding to the bar code. The signal transceiver and the electromagnetic pen are electrically connected to the host device. The electromagnetic pen is used to make a mark on a scrap region of the circuit board where any defect is visually found through the microscope. The signal transceiver receives and transmits the positions of the mark to the host device such that the host device calculates the coordinate of a scrap region based on a relative position between an original point and the positions of the mark.
摘要翻译：公开了一种最终缺陷检查系统，其包括主机，显微镜，条形码扫描器，支持工具，信号收发器和电磁笔。条形码扫描器扫描设置在支撑板上的电路板上的条形码。主机设备从与条形码对应的数据库中选择数据和电路布局图。信号收发器和电磁笔电连接到主机设备。电磁笔用于在电路板的废料区域上形成标记，其中通过显微镜在视觉上发现任何缺陷。信号收发器接收和发送标记的位置到主机设备，使得主机设备基于原始点和标记位置之间的相对位置来计算废料区域的坐标。

82. 发明授权

US08471375B2 High-density fine line structure and method of manufacturing the same 有权
标题翻译：高密度细线结构及其制造方法
公开(公告)号：US08471375B2
公开(公告)日：2013-06-25
申请号：US11772208
申请日：2007-06-30
申请人： Chien-Wei Chang , Ting-Hao Lin
发明人： Chien-Wei Chang , Ting-Hao Lin
IPC分类号： H01L23/02
CPC分类号： H01L21/4846 , H01L21/565 , H01L21/6835 , H01L24/16 , H01L24/48 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/81001 , H01L2224/81801 , H01L2225/0651 , H01L2225/06517 , H01L2225/06582 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/181 , H05K1/186 , H05K3/205 , H05K2201/10515 , H05K2201/10674 , H05K2203/049 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density.
摘要翻译：高密度细线结构主要包括：具有相似结构的两个板和用于梳理两个板的电介质膜。两块板之间的半导体器件相互相对，两块板组合起来。两个板各自包括细线电路，同一表面上的绝缘层，以及安装在细线电路上方的半导体器件。未被焊接掩模覆盖的电路的表面被制成焊盘。衬垫填充有用于与另一半导体器件电连接的锡球。使用电镀而不是蚀刻方法来形成细线电路层，并且去除在制造过程期间或结束时需要的载体和金属阻挡层，以增加用于实现该目的的物体的布线密度高密度。

83. 发明授权

US07871892B2 Method for fabricating buried capacitor structure 有权
标题翻译：掩埋电容器结构的制造方法
公开(公告)号：US07871892B2
公开(公告)日：2011-01-18
申请号：US12479811
申请日：2009-06-07
申请人： Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen , Yu-Te Lu
发明人： Chien-Wei Chang , Ting-Hao Lin , Ya-Hsiang Chen , Yu-Te Lu
IPC分类号： H01L21/20
CPC分类号： B32B37/02 , B32B38/06 , B32B2038/047 , B32B2457/08 , B32B2457/16 , H01G4/236 , H01G4/33 , H05K1/162 , H05K3/4602 , H05K2201/09236 , H05K2201/09509 , H05K2203/1461
摘要： A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.
摘要翻译：一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠，在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

84. 发明授权

US07807034B2 Manufacturing method of non-etched circuit board 有权
标题翻译：非蚀刻电路板的制造方法
公开(公告)号：US07807034B2
公开(公告)日：2010-10-05
申请号：US11734274
申请日：2007-04-12
申请人： Ting-Hao Lin
发明人： Ting-Hao Lin
IPC分类号： C25D5/02
CPC分类号： H05K3/423 , H05K3/0035 , H05K3/025 , H05K3/205 , H05K3/242 , H05K3/382 , H05K3/421 , H05K2201/09563 , H05K2203/0376 , H05K2203/0384 , H05K2203/0554 , H05K2203/1152
摘要： A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained.
摘要翻译：本文公开了一种未蚀刻电路板的制造方法，其采用具有金属阻挡层和电镀铜层的金属基板来传输电流以形成电路层。在电镀铜层上形成图案化的光致抗蚀剂层以限定电路层的位置，并通过电镀在电路板上形成电路或导电通孔。在电路层上进一步形成电镀镍层或电镀金层，以保护电路并提高细线能力。在处理过程中或之后，去除金属基板，金属阻挡层和电镀铜层以扩大布线空间，从而可以获得高密度电路板。

85. 发明授权

US07405146B2 Electroplating method by transmitting electric current from a ball side 有权
标题翻译：从球侧传输电流的电镀方法
公开(公告)号：US07405146B2
公开(公告)日：2008-07-29
申请号：US11338376
申请日：2006-01-24
申请人： Cheng-Kuo Ma
发明人： Cheng-Kuo Ma
IPC分类号： H01L21/445
CPC分类号： H05K3/243 , H05K3/062 , H05K3/242 , H05K3/28 , H05K2201/0352 , H05K2203/1476 , H05K2203/1581 , Y10T29/49124 , Y10T29/49165
摘要： An electroplating method by transmitting electric current from a ball side is provided. In the electroplating method, the circuit layer is firstly formed on the bump side of the IC board, and the electric current is transmitted to the portion of the circuit layer uncovered by the insulating layer formed on the bump side from the electroplated metal layer on the ball side to form the protective layer (the electroplated gold layer) on the portion of the circuit layer. In such a way, the electroplated gold layer cannot be formed under the insulating layer formed on the bump side (attached with the chip) because the electroplated gold layer is formed after the insulating layer has been formed, and thereby the fall-off of the insulating layer from the electroplated gold layer will not happen. Therefore, the reliability of the products is enhanced.
摘要翻译：提供了通过从球侧传输电流的电镀方法。在电镀方法中，电路层首先形成在IC板的凸块侧，并且电流被传导到电路层的未被凸起侧形成的绝缘层的电镀层的电镀层上的电镀金属层球侧，以在电路层的部分上形成保护层（电镀金层）。以这种方式，由于在形成绝缘层之后形成电镀金层，所以不能在形成在凸块侧（附着芯片）的绝缘层的下方形成电镀金层，从而使电镀金层脱落绝缘层与电镀金层不会发生。因此，提高了产品的可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式