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81. 发明授权

US09368221B2 Switch and semiconductor device including the switch 有权
标题翻译：开关和半导体器件包括开关
公开(公告)号：US09368221B2
公开(公告)日：2016-06-14
申请号：US14493675
申请日：2014-09-23
申请人： PS4 LUXCO S.A.R.L.
发明人： Stefano Sivero , Chiara Missiroli
IPC分类号： G11C16/22 , H03K17/10 , G11C16/12 , H03K3/356
CPC分类号： G11C16/22 , G11C16/12 , H03K3/356182 , H03K17/102 , H03K2217/0054 , H03K2217/0081
摘要： A device for use with non-volatile memory, includes a first transistor of a first channel type coupled between first and second nodes, including a control gate supplied with a first control signal having a first phase, a second transistor of a second channel type different from the first channel type including a first terminal coupled to the first node, a second terminal coupled to a third node, a back gate coupled to the first terminal thereof, and a control gate supplied with a second control signal having a second phase substantially opposite to the first phase, a third transistor of the second channel type including a first terminal coupled to the second node, a second terminal coupled to the third node, a back gate coupled to the first terminal thereof, and a control gate supplied with the second control signal, and a protection circuit coupled between the first and second node.
摘要翻译：一种与非易失性存储器一起使用的装置，包括耦合在第一和第二节点之间的第一通道类型的第一晶体管，包括提供有具有第一相位的第一控制信号的控制栅极，第二通道类型不同的第二晶体管从包括耦合到第一节点的第一端子的第一通道类型，耦合到第三节点的第二端子，耦合到其第一端子的后栅极和提供有第二控制信号的控制栅极，第二控制信号具有基本相反的第二相位第二通道类型的第三晶体管包括耦合到第二节点的第一端子，耦合到第三节点的第二端子，耦合到其第一端子的后栅极和提供有第二端子的控制栅极控制信号和耦合在第一和第二节点之间的保护电路。

82. 发明授权

US09362288B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09362288B2
公开(公告)日：2016-06-07
申请号：US14427964
申请日：2013-09-06
申请人： PS4 LUXCO S.A.R.L.
发明人： Mitsunari Sukekawa
IPC分类号： H01L21/00 , H01L27/00 , H01L29/00 , H01L27/108 , H01L21/768 , H01L29/66 , H01L29/78
CPC分类号： H01L27/10823 , H01L21/76897 , H01L27/10808 , H01L27/10814 , H01L27/10826 , H01L27/10855 , H01L27/10876 , H01L27/10879 , H01L27/10885 , H01L27/10888 , H01L29/66666 , H01L29/7827
摘要： One semiconductor device includes an active region extending in a first direction, and first, second, and third semiconductor pillars which are provided upright relative to a main surface of the active region and disposed side by side in succession in the first direction; and between the first semiconductor pillar and the second semiconductor pillar, a first gate insulating film in contact with a side surface of the first semiconductor pillar, a first gate electrode in contact with the first gate insulating film, a second gate insulating film in contact with a side surface of the second semiconductor pillar, a second gate electrode in contact with the second gate insulating film, and a first embedded insulating film located between the first and second gate electrodes; and between the second and third semiconductor pillars, a second embedded insulating film in contact with the side surfaces of the second and third semiconductor pillars.
摘要翻译：一个半导体器件包括沿第一方向延伸的有源区，以及第一，第二和第三半导体柱，所述第一，第二和第三半导体柱相对于有源区的主表面竖立设置，并且在第一方向上并排设置; 并且在第一半导体柱和第二半导体柱之间，与第一半导体柱的侧面接触的第一栅极绝缘膜，与第一栅极绝缘膜接触的第一栅极电极，与第一栅极绝缘膜接触的第二栅极绝缘膜第二半导体柱的侧表面，与第二栅极绝缘膜接触的第二栅电极和位于第一和第二栅电极之间的第一嵌入绝缘膜; 并且在第二和第三半导体柱之间，与第二和第三半导体柱的侧表面接触的第二嵌入绝缘膜。

83. 发明授权

US09331144B2 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09331144B2
公开(公告)日：2016-05-03
申请号：US14426143
申请日：2013-09-03
申请人： PS4 Luxco S.a.r.l.
发明人： Shingo Ujihara , Koji Taniguchi
IPC分类号： H01L29/00 , H01L29/06 , H01L27/108 , H01L21/762 , H01L21/76
CPC分类号： H01L29/0649 , H01L21/76 , H01L21/76224 , H01L21/76229 , H01L27/10894
摘要： A semiconductor device includes, on one semiconductor substrate: a first element isolation region having a first width, wherein a liner oxide film, a liner nitride film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the first element isolation region; and a second element isolation region having a second width that is larger than the first width, wherein a liner oxide film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the second element isolation region.
摘要翻译：半导体器件包括：在一个半导体衬底上：具有第一宽度的第一元件隔离区域，其中衬垫氧化物膜，衬里氮化物膜和二氧化硅膜从所述第一宽度的上表面的外周侧连续地设置第一元件隔离区; 以及具有大于第一宽度的第二宽度的第二元件隔离区域，其中从第二元件隔离区域的上表面的外周侧依次提供衬垫氧化物膜和二氧化硅膜。

84. 发明授权

US09331138B2 Semiconductor device having storage electrode and manufacturing method thereof 有权
标题翻译：具有存储电极的半导体器件及其制造方法
公开(公告)号：US09331138B2
公开(公告)日：2016-05-03
申请号：US14265254
申请日：2014-04-29
申请人： PS4 Luxco S.a.r.l.
发明人： Takashi Miyajima
IPC分类号： H01L27/108 , H01L49/02 , H01L27/06 , H01L21/768 , H01L23/532
CPC分类号： H01L28/60 , H01L21/76804 , H01L21/76895 , H01L23/53257 , H01L27/0688 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L28/90 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first storage electrode, a second storage electrode that is arranged above the first storage electrode, a first landing pad that is arranged between a top surface of the first storage electrode and a bottom surface of the second storage electrode, the first landing pad connecting the first storage electrode and the second storage electrode, the first landing pad having a first landing surface, the first landing surface being larger than the bottom surface of the second storage electrode, and the second storage electrode being placed on the first landing surface, a capacitive insulating film that is laminated on the first and second storage electrodes and on an outer circumferential surface of the first landing pad, and a plate electrode that contacts the capacitive insulating film.
摘要翻译：半导体器件包括第一存储电极和布置在第一存储电极上方的第二存储电极，布置在第一存储电极的顶表面和第二存储电极的底表面之间的第一着地焊盘，第一存储电极连接第一存储电极和第二存储电极的着陆焊盘，第一着陆焊盘具有第一着陆表面，第一着陆表面大于第二存储电极的底表面，并且第二存储电极放置在第一着陆层叠在第一和第二存储电极上以及第一着陆焊盘的外周面上的电容绝缘膜和与电容绝缘膜接触的平板电极。

85. 发明授权

US09305926B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09305926B2
公开(公告)日：2016-04-05
申请号：US14628724
申请日：2015-02-23
申请人： PS4 Luxco S.a.r.l.
发明人： Hiroaki Taketani
IPC分类号： H01L27/108 , H01L21/762 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/10 , H01L29/49
CPC分类号： H01L27/10823 , H01L21/76224 , H01L27/108 , H01L27/10814 , H01L27/10829 , H01L27/10876 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1025 , H01L29/1095 , H01L29/4236 , H01L29/4916 , H01L29/4966 , H01L29/7827
摘要： A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.
摘要翻译：包括半导体器件的半导体器件可以包括但不限于半导体衬底，隔离电极，栅极电极，栅极绝缘膜和第一绝缘膜。半导体衬底具有第一凹槽和第二凹槽。隔离电极位于第一槽中。栅电极位于第二槽中。栅极绝缘膜与栅电极相邻。第一绝缘膜与隔离电极相邻。隔离电极的阈值电压比栅电极大。

86. 发明授权

US09293190B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09293190B2
公开(公告)日：2016-03-22
申请号：US14618076
申请日：2015-02-10
申请人： PS4 LUXCO S.A.R.L.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/4093 , G11C11/4091 , G11C5/02 , G11C7/08 , G11C7/10 , G11C11/4096
CPC分类号： G11C11/4093 , G11C5/025 , G11C7/08 , G11C7/1051 , G11C7/1069 , G11C11/4091 , G11C11/4096 , G11C2207/005
摘要： A semiconductor includes a plurality of memory cell arrays each of which includes a plurality of memory cells. Bitlines extend in one direction in the memory cell arrays to transfer data stored in the memory cells. Wordlines extend perpendicular to the bitlines in the memory cell arrays to select at least one of the memory cells. Local data lines extend parallel to the wordlines outside of the memory cell arrays and convey signals from bitlines. Global data lines convey signals from the local data lines. The global data lines include a part extending parallel to the wordlines and the part is disposed over another one of the memory cell arrays other than a selected memory cell array.
摘要翻译：半导体包括多个存储单元阵列，每个存储单元阵列包括多个存储单元。位线在存储单元阵列中沿一个方向延伸，以传输存储在存储单元中的数据。字线垂直于存储单元阵列中的位线延伸，以选择至少一个存储单元。本地数据线与存储单元阵列外的字线平行延伸，并从位线传送信号。全局数据线传输来自本地数据线的信号。全局数据线包括平行于字线延伸的部分，并且部分被布置在存储单元阵列之外，而不是所选存储单元阵列。

87. 发明申请

US20160064301A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160064301A1
公开(公告)日：2016-03-03
申请号：US14784632
申请日：2014-04-11
申请人： Atsushi TOMOHIRO , PS4 LUXCO S.A.R.L.
发明人： Atsushi Tomohiro
IPC分类号： H01L23/367 , H01L23/31 , H05K1/18 , H05K1/11 , H01L25/10 , H01L23/498 , H05K1/02
CPC分类号： H01L23/3675 , H01L21/561 , H01L23/3107 , H01L23/3128 , H01L23/3677 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/10161 , H01L2924/1436 , H01L2924/15182 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/0206 , H05K1/0209 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09781 , H05K2203/049 , H01L2224/83 , H01L2224/85 , H01L2224/16225 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： One semiconductor device includes a wiring board, a semiconductor chip, and an encapsulation body. The wiring board includes an insulating base, a conductive pattern that is formed on one surface of the insulating base, and a heat dissipation via that is connected to the conductive pattern. The heat dissipation via is provided so as to penetrate through the insulating base from one surface to the other surface, while being exposed from the lateral side of the insulating base. The semiconductor chip is mounted on the wiring board so as to overlap the conductive pattern. The encapsulation body is formed on the wiring board so as to cover the semiconductor chip.
摘要翻译：一个半导体器件包括布线板，半导体芯片和封装体。布线板包括绝缘基底，形成在绝缘基底的一个表面上的导电图案和连接到导电图案的散热通孔。散热通孔设置成从绝缘基体的侧面露出而从一个表面穿过绝缘基底到另一个表面。半导体芯片安装在布线板上以与导电图案重叠。封装体形成在布线板上以覆盖半导体芯片。

88. 发明授权

US09263456B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09263456B2
公开(公告)日：2016-02-16
申请号：US13533598
申请日：2012-06-26
申请人： Kanta Saino
发明人： Kanta Saino
IPC分类号： H01L27/108 , H01L27/105
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10852 , H01L27/10873 , H01L27/10885
摘要： A semiconductor device comprises a semiconductor substrate, a first transistor including a gate insulating film and a gate electrode sequentially formed on the semiconductor substrate, a sidewall, an interlayer insulating film formed on the semiconductor substrate, and a contact plug which penetrates through the interlayer insulating film and reaches the semiconductor substrate. The sidewall is formed on a side surface of the gate electrode, and includes a first insulating film and a second insulating film formed on the first insulating film and containing a metal oxide different from the first insulating film.
摘要翻译：半导体器件包括半导体衬底，第一晶体管，包括栅极绝缘膜和依次形成在半导体衬底上的栅电极，侧壁，形成在半导体衬底上的层间绝缘膜，以及穿过层间绝缘层的接触插塞并到达半导体衬底。侧壁形成在栅电极的侧表面上，并且包括形成在第一绝缘膜上并包含不同于第一绝缘膜的金属氧化物的第一绝缘膜和第二绝缘膜。

89. 发明授权

US09236387B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09236387B2
公开(公告)日：2016-01-12
申请号：US14186369
申请日：2014-02-21
申请人： PS4 LUXCO S.A.R.L.
发明人： Kiyonori Oyu , Kensuke Okonogi , Kazuto Mori
IPC分类号： H01L27/108 , H01L29/78 , H01L29/423 , H01L29/66 , H01L29/10 , H01L29/08
CPC分类号： H01L27/10823 , H01L27/10876 , H01L29/0847 , H01L29/1037 , H01L29/4236 , H01L29/42368 , H01L29/66621 , H01L29/78 , H01L29/7827
摘要： A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.
摘要翻译：一种半导体器件，其能够在降低沟道电阻的同时增加导通电流，并允许晶体管独立且稳定地工作，其具有形成为从栅电极沟槽的底部突出的鳍状物，覆盖栅电极沟槽的表面的栅绝缘膜和鳍状物，嵌入在栅极电极沟槽的下部并形成为经由栅极绝缘膜跨越翅片的栅电极，布置在第一侧面上的第一杂质扩散区域和布置在第二侧面上的第二杂质扩散区域侧面。

90. 发明授权

US09236149B2 Semiconductor device having hierarchically structured bit lines 有权
标题翻译：具有分层结构的位线的半导体器件
公开(公告)号：US09236149B2
公开(公告)日：2016-01-12
申请号：US13964782
申请日：2013-08-12
申请人： PS4 Luxco S.a.r.l.
发明人： Noriaki Mochida
IPC分类号： G11C29/00 , G11C11/4097
CPC分类号： G11C29/76 , G11C5/06 , G11C11/4097 , G11C29/808
摘要： Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.
摘要翻译：本文公开了一种包括第一和第二存储器垫的装置。第一存储器堆包括耦合到第一全局位线的第一缺陷存储器单元和第一本地位线。第一局部位线中的每一个被耦合到相关联的第一存储单元，第一局部位线中的一个进一步耦合到有缺陷的存储单元。第二存储器垫包括耦合到第二全局位线的第二和冗余存储器单元和第二本地位线。第二本地位线中的每一个被耦合到相关联的第二存储器单元，其中一个第二局部位线进一步耦合到冗余存储单元。该设备还包括当访问地址信息与指定有缺陷的存储器单元的缺陷地址信息一致时，访问冗余存储单元的控制电路。

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