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81. 发明授权

US07474662B2 Systems and methods for rate-limited weighted best effort scheduling 失效
标题翻译：速率限制加权最佳努力调度的系统和方法
公开(公告)号：US07474662B2
公开(公告)日：2009-01-06
申请号：US11119329
申请日：2005-04-29
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/623 , H04L47/50 , H04L47/568
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，四入口日历结构提供速率受限加权最佳努力调度。多个不同流中的每一个都具有相关联的调度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块都有一个计数器，并根据相应数据包所属的流的带宽优先级分配速率限制。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其速率限制时，调度控制块暂时从进一步调度中移除，直到时间间隔结束。

82. 发明申请

US20080307439A1 REDUCING MEMORY ACCESSES IN PROCESSING TCP/IP PACKETS 失效
标题翻译：减少处理TCP / IP分组中的内存访问
公开(公告)号：US20080307439A1
公开(公告)日：2008-12-11
申请号：US12185101
申请日：2008-08-03
申请人： Claude Basso , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen
发明人： Claude Basso , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen
IPC分类号： G06F9/44
CPC分类号： H04L69/16 , H04L69/163
摘要： A method, computer program product and system for processing TCP/IP packets. A TCP protocol stack may store a payload of a received TCP/IP packet in a data fragment list. The TCP protocol stack may further read the header of the received packet to extract a value used to index into a table storing a list of transport control blocks (TCBs). The TCP protocol stack may further perform a lock and a read operation on the TCB indexed in the table. The TCP protocol stack may further transmit the payload to the TCP application without requiring the application to perform a lock, read, write or unlock operation on the indexed TCB since the TCP protocol stack and the TCP application are operating on the same thread. By the TCP application foregoing the lock, read, write and unlock operations on the TCB, there is a reduction in the number of memory accesses.
摘要翻译：一种用于处理TCP / IP数据包的方法，计算机程序产品和系统。 TCP协议栈可以将接收到的TCP / IP分组的有效载荷存储在数据片段列表中。 TCP协议栈可以进一步读取接收到的分组的报头，以将用于索引的值提取到存储传输控制块（TCB）列表的表中。 TCP协议栈还可以对表中索引的TCB进行锁定和读取操作。 TCP协议栈可以进一步将有效负载传输到TCP应用，而不需要应用程序对索引的TCB执行锁定，读取，写入或解锁操作，因为TCP协议栈和TCP应用程序在相同的线程上运行。通过TCP应用程序对TCB进行锁定，读取，写入和解锁操作，存储器访问次数减少。

83. 发明授权

US07436853B2 Reducing memory accesses in processing TCP/IP packets 失效
标题翻译：在处理TCP / IP数据包时减少内存访问
公开(公告)号：US07436853B2
公开(公告)日：2008-10-14
申请号：US10706235
申请日：2003-11-12
申请人： Claude Basso , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen
发明人： Claude Basso , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen
IPC分类号： H04J3/22
CPC分类号： H04L69/16 , H04L69/163
摘要： A method, computer program product and system for processing TCP/IP packets. A TCP protocol stack may store a payload of a received TCP/IP packet in a data fragment list. The TCP protocol stack may further read the header of the received packet to extract a value used to index into a table storing a list of transport control blocks (TCBs). The TCP protocol stack may further perform a lock and a read operation on the TCB indexed in the table. The TCP protocol stack may further transmit the payload to the TCP application without requiring the application to perform a lock, read, write or unlock operation on the indexed TCB since the TCP protocol stack and the TCP application are operating on the same thread. By the TCP application foregoing the lock, read, write and unlock operations on the TCB, there is a reduction in the number of memory accesses.
摘要翻译：一种用于处理TCP / IP数据包的方法，计算机程序产品和系统。 TCP协议栈可以将接收到的TCP / IP分组的有效载荷存储在数据片段列表中。 TCP协议栈可以进一步读取接收到的分组的报头，以将用于索引的值提取到存储传输控制块（TCB）列表的表中。 TCP协议栈还可以对表中索引的TCB进行锁定和读取操作。 TCP协议栈可以进一步将有效负载传输到TCP应用，而不需要应用程序对索引的TCB执行锁定，读取，写入或解锁操作，因为TCP协议栈和TCP应用程序在相同的线程上运行。通过TCP应用程序对TCB进行锁定，读取，写入和解锁操作，存储器访问次数减少。

84. 发明授权

US07409520B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07409520B2
公开(公告)日：2008-08-05
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

85. 发明申请

US20080147995A1 SYSTEMS AND METHODS FOR MULTI-FRAME CONTROL BLOCKS 有权
标题翻译：多框控制块的系统和方法
公开(公告)号：US20080147995A1
公开(公告)日：2008-06-19
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

86. 发明授权

US07304991B2 Minimizing memory accesses for a network implementing differential services over multi-protocol label switching 失效
标题翻译：最小化通过多协议标签交换实现差分服务的网络的存储器访问
公开(公告)号：US07304991B2
公开(公告)日：2007-12-04
申请号：US10174390
申请日：2002-06-18
申请人： Claude Basso , Francis Arts , Brahmanand Kumar Gorti , Colin Beaton Verrilli
发明人： Claude Basso , Francis Arts , Brahmanand Kumar Gorti , Colin Beaton Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L47/2491 , H04L47/10 , H04L47/17 , H04L47/2408 , H04L47/2416
摘要： A method, system and computer program product for translating a type of service field of one protocol into multiple protocols. An ingress router in a DIFFerentiated SERVices network (Diffserv over MPLS network) may determine a type of quality of service, e.g., forward IP packet using best effort. A value referred to as a Per Hope Behavior (PHB) value may be generated based on the identified type of quality of service. The PHB value may be used to index into a table comprising a row of entries with different quality of service values, e.g., DSCP value, EXP value, corresponding to a particular PHB value. Consequently, the PHB value may be used to perform a single memory access to determine the quality of service values for a plurality of protocols where the quality of service values corresponds to the identified type of quality of service.
摘要翻译：一种方法，系统和计算机程序产品，用于将一种协议的服务领域的类型转换为多种协议。 DIFFerentiated SERVices网络中的入侵路由器（MPLS网络上的Diffserv）可以使用最大的努力来确定服务质量的类型，例如转发IP分组。可以基于所识别的服务质量类型来生成被称为希望行为（PHB）值的值。 PHB值可以用于索引到包括具有不同服务质量值的条目行的表，例如对应于特定PHB值的DSCP值，EXP值。因此，PHB值可用于执行单个存储器访问以确定多个协议的服务质量值，其中服务质量值对应于所识别的服务质量类型。

87. 发明授权

US07280527B2 Logically grouping physical ports into logical interfaces to expand bandwidth 失效
标题翻译：将物理端口逻辑分组为逻辑接口以扩展带宽
公开(公告)号：US07280527B2
公开(公告)日：2007-10-09
申请号：US10144075
申请日：2002-05-13
申请人： Claude Basso , Francis Arts , Bay Van Nguyen , Natarajan Vaidhyanathan , Colin Beaton Verrilli
发明人： Claude Basso , Francis Arts , Bay Van Nguyen , Natarajan Vaidhyanathan , Colin Beaton Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L45/54 , H04L45/00 , H04L45/24
摘要： A method, system and computer program product for routing packets. A network device, e.g., router, may comprise a switch fabric coupled to a plurality of blades where each blade may comprise one or more network processors coupled to one or more physical ports. The physical ports may be connected to another one or more network devices. A plurality of physical ports across one or more blades connected to the same network device may be logically mapped into a logical interface to that network device. By logically grouping a plurality of physical ports into a logical interface to a network device, a network processor may be able to transmit packets of data to that network device across multiple ports instead of one physical port.
摘要翻译：用于路由数据包的方法，系统和计算机程序产品。网络设备（例如，路由器）可以包括耦合到多个叶片的交换结构，其中每个叶片可以包括耦合到一个或多个物理端口的一个或多个网络处理器。物理端口可以连接到另一个或多个网络设备。连接到同一网络设备的一个或多个刀片上的多个物理端口可以逻辑地映射到该网络设备的逻辑接口中。通过将多个物理端口逻辑地分组成到网络设备的逻辑接口，网络处理器可能能够跨多个端口而不是一个物理端口向该网络设备传送数据分组。

88. 发明授权

US07177951B1 Address management in PNNI hierarchical networks 有权
标题翻译： PNNI分层网络中的地址管理
公开(公告)号：US07177951B1
公开(公告)日：2007-02-13
申请号：US09625624
申请日：2000-07-26
申请人： Douglas Dykeman , Michael Osbourne , Paolo Scotton , Olen Stokes , Claude Basso , Marianne Aubry , Minh-Tri Do Khac
发明人： Douglas Dykeman , Michael Osbourne , Paolo Scotton , Olen Stokes , Claude Basso , Marianne Aubry , Minh-Tri Do Khac
IPC分类号： G06F15/16
CPC分类号： H04L29/12254 , H04L29/12009 , H04L29/12783 , H04L29/12801 , H04L41/0893 , H04L41/12 , H04L45/02 , H04L45/04 , H04L49/3081 , H04L61/2038 , H04L61/35 , H04L61/6004 , H04L2012/5621 , H04L2012/5627 , H04L2012/5685 , H04Q11/0478
摘要： Address management methods and apparatus are provided for a node serving as peer group leader for a peer group of nodes in one level of the hierarchy of a PNNI hierarchical network, whereby the peer group leader represents the peer group to one or more neighboring nodes in the next level up of the hierarchy. The peer group leader has a memory (2) for storing peer group topology data (4), comprising address data which is supplied to the peer group leader from nodes in the peer group and represents addresses for access by the network, and peer group leader topology data (5), comprising address data which is supplied to said neighboring nodes by the peer group leader and represents addresses accessible via the peer group. The address management method comprises: checking whether addresses represented by said address data are accessible via the peer group; notifying said neighboring nodes of changes in the accessibility of addresses so identified; and updating said peer group leader topology data (5) in accordance with said changes.
摘要翻译：为PNNI分级网络的层级的一个级别中的对等组节点作为对等组组长的节点提供地址管理方法和装置，由此对等组组长表示对等体组到一个或多个相邻节点下一级别的层次结构。对等组组长具有用于存储对等组群拓扑数据（4）的存储器（2），包括从对等组中的节点提供给对等组组长的地址数据，表示网络接入的地址和对等组组长拓扑数据（5），包括由对等组组长提供给所述相邻节点并且表示经由对等组可访问的地址的地址数据。地址管理方法包括：检查由所述地址数据表示的地址是否可通过对等体组访问; 通知所述相邻节点对所识别的地址的可访问性的变化; 以及根据所述改变更新所述对等群组领导拓扑数据（5）。

89. 发明申请

US20060222002A1 Configurable ports for a host Ethernet adapter 失效
标题翻译：适用于主机以太网适配器的可配置端口
公开(公告)号：US20060222002A1
公开(公告)日：2006-10-05
申请号：US11097652
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
IPC分类号： H04J3/22 , H04J3/16
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

90. 发明申请

US20060221969A1 System and method for computing a blind checksum in a host ethernet adapter (HEA) 失效
公开(公告)号：US20060221969A1
公开(公告)日：2006-10-05
申请号：US11097430
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
IPC分类号： H04L12/28
CPC分类号： H04L69/16 , H04L69/161
摘要： A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of the packet. If the packet is in IPv4, the system determines whether the packet is in transmission control protocol (TCP) or user datagram protocol (UDP). If the packet is not in either of TCP or UDP the system attaches a pseudo-header to the packet and computes the checksum of the packet based on the pseudo-header and the IPv4 standard.

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