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81. 发明授权

US6047396A Digital data storage system including phantom bit storage locations 失效
标题翻译：数字数据存储系统包括幻影位存储位置
公开(公告)号：US6047396A
公开(公告)日：2000-04-04
申请号：US548799
申请日：1995-11-02
申请人： W. Daniel Hillis
发明人： W. Daniel Hillis
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A digital data storage arrangement includes a storage register for storing a data word having a predetermined number of data bits along with an error correction code, a data input circuit and a data output circuit. The data input circuit receives an input data word having a number of data bits with at most a selected larger number of data bits than can be stored in said storage register, and generates an error correction code value in response to all of the data bits of said input data word. The data input circuit couples the data word, comprising the predetermined number of data bits of the input data word, along with the error correction code value for storage in the storage register. Thus, if the number of bits of the input data word exceeds the predetermined number of bits that can be stored in the storage register, the storage register only stores the predetermined number of data bits, not all of the bits of the input data word. The data output circuit retrieves the data word and the error correction code from storage register and using the error correction code, generates an output data word which corresponding to the input data word provided by the data input circuit. In particular, the error correction code permits the data output circuit to generate an output data word that includes, in addition to the portion of the input data word that was stored in the storage register, the missing bits that were not stored in the storage register.
摘要翻译：数字数据存储装置包括存储寄存器，用于存储具有预定数量的数据位以及纠错码的数据字，数据输入电路和数据输出电路。数据输入电路接收输入数据字，该输入数据字具有多于最多可以存储在所述存储寄存器中的选定数量的数据位数的数据位，并响应于所有数据位的数据位产生纠错码值所述输入数据字。数据输入电路将包括输入数据字的预定数量的数据位的数据字与纠错码值一起耦合，以存储在存储寄存器中。因此，如果输入数据字的位数超过可以存储在存储寄存器中的预定位数，则存储寄存器仅存储预定数量的数据位，而不是所有输入数据字的所有位。数据输出电路从存储寄存器检索数据字和纠错码，并使用纠错码产生与数据输入电路提供的输入数据字对应的输出数据字。特别地，纠错码允许数据输出电路产生输出数据字，除了存储在存储寄存器中的输入数据字的部分之外，还包括未存储在存储寄存器中的丢失位。

82. 发明授权

US5978570A Memory system providing page mode memory access arrangement 失效
标题翻译：内存系统提供页面模式内存访问安排
公开(公告)号：US5978570A
公开(公告)日：1999-11-02
申请号：US387990
申请日：1995-02-13
申请人： W. Daniel Hillis
发明人： W. Daniel Hillis
IPC分类号： G06F15/16 , G06F9/38 , G06F9/50 , G06F11/16 , G06F12/02 , G06F12/10 , G06F15/173 , G06F15/177 , G06F15/80 , G06F12/06
CPC分类号： G06F9/5066 , G06F12/0215 , G06F15/17343 , G06F15/17381 , G06F15/8023 , G06F15/803 , G06F9/3836 , G06F9/5077 , G06F11/165 , G06F11/1658 , G06F11/2041 , G06F11/2046 , G06F11/2094 , G06F12/10
摘要： A method and apparatus are described for improving the utilization of a parallel computer by allocating the resources of the parallel computer among a large number of users. A parallel computer is subdivided among a large number of users to meet the requirements of a multiplicity of databases and programs that are run simultaneously on the computer. This is accomplished by dividing the parallel computer into a plurality of processor arrays, each of which can be used independently of the others. This division is made dynamically in the sense that the division can readily be altered and indeed in a time sharing environment may be altered between two successive time slots of the frame. Further, the parallel computer is organized so as to permit the simulation of additional parallel processors by each physical processor in the array and to provide for communication among the simulated parallel processors. This parallel computer also provides for storage of virtual processors in virtual memory. As a result of this design, it is possible to build a parallel computer with a number of physical processors on the order of 1,000,000 and a number of virtual processors on the order of 1,000,000,000,000. Moreover, since the computer can be dynamically reconfigured into a plurality of independent processor arrays, a device this size can be shared by a large number of users with each user operating on only a portion of the entire computer having a capacity appropriate for the problem then being addressed.
摘要翻译：描述了通过在大量用户中分配并行计算机的资源来提高并行计算机的利用率的方法和装置。并行计算机被划分成大量用户，以满足在计算机上同时运行的多个数据库和程序的要求。这通过将并行计算机分成多个处理器阵列来实现，每个处理器阵列可以独立于其他阵列使用。在划分可以容易地改变并且实际上在时间共享环境可以在帧的两个连续时隙之间被改变的意义上来动态地进行划分。此外，并行计算机被组织以便允许由阵列中的每个物理处理器模拟额外的并行处理器，并提供模拟的并行处理器之间的通信。该并行计算机还提供虚拟处理器在虚拟内存中的存储。作为此设计的结果，可以构建具有大量1,000,000个物理处理器的并行计算机和大约1,000,000,000,000个的虚拟处理器。而且，由于计算机可以被动态地重新配置成多个独立的处理器阵列，所以这个大小的设备可以由大量的用户共享，每个用户仅在整个计算机的一部分上运行，具有适合该问题的容量被处理。

83. 发明授权

US5913070A Inter-connector for use with a partitionable massively parallel processing system 失效
标题翻译：用于可分割的大规模并行处理系统的连接器
公开(公告)号：US5913070A
公开(公告)日：1999-06-15
申请号：US587184
申请日：1996-01-16
申请人： W. Daniel Hillis
发明人： W. Daniel Hillis
IPC分类号： G06F9/50 , G06F15/173 , G06F15/80
CPC分类号： G06F9/5066 , G06F15/17343 , G06F9/5077
摘要： Apparatus is described for allocating the resources of a parallel computer. The computer is divided into a plurality of processor arrays, a plurality of host computers are provided, and the host computers and the arrays are interfaced by an interconnection means that can connect any host computer to any one or more of the arrays. A specific connection means comprises a plurality of first multiplexers, one for each array, for writing data from any host computer to any array; a plurality of second multiplexers, one for each host computer, for reading from any array to any host computer; and control means for controlling the multiplexers so as to connect the host computers and arrays as desired by the users. The control means comprises a status register which specifies the connections between the host computers and the processor arrays as specified by the users.
摘要翻译：描述了用于分配并行计算机的资源的装置。计算机被分成多个处理器阵列，提供多个主计算机，并且主计算机和阵列通过互连装置接口，该互连装置可以将任何主计算机连接到任何一个或多个阵列。特定连接装置包括多个第一复用器，每个阵列一个，用于将数据从任何主机写入任何阵列; 多个第二多路复用器，每个主计算机一个，用于从任何阵列读取到任何主计算机; 以及控制装置，用于控制多路复用器，以便根据用户的需要连接主计算机和阵列。控制装置包括状态寄存器，其指定用户指定的主计算机和处理器阵列之间的连接。

84. 发明授权

US5202979A Storage system using multiple independently mechanically-driven storage units 失效
标题翻译：存储系统使用多个独立的机械驱动存储单元
公开(公告)号：US5202979A
公开(公告)日：1993-04-13
申请号：US906006
申请日：1992-06-26
申请人： W. Daniel Hillis , Clement K. Liu
发明人： W. Daniel Hillis , Clement K. Liu
IPC分类号： G11B20/18
CPC分类号： G11B20/1833
摘要： A storage system for data words in which error correction bits are generated for each data word and are stored independently from the data word on a separate mechanically-driven medium. In another aspect, the storage system serves a wide high throughput parallel bus by storing different portions of each data word that appears on the bus in different asynchronous storage units.
摘要翻译：用于数据字的存储系统，其中为每个数据字生成纠错位，并且在单独的机械驱动介质上独立于数据字存储。在另一方面，存储系统通过在不同的异步存储单元中存储出现在总线上的每个数据字的不同部分来服务于宽的高吞吐量并行总线。

85. 发明授权

US5175865A Partitioning the processors of a massively parallel single array processor into sub-arrays selectively controlled by host computers 失效
标题翻译：将大容量并行单阵列处理器的处理器分区为由主机计算机选择性控制的子阵列
公开(公告)号：US5175865A
公开(公告)日：1992-12-29
申请号：US725395
申请日：1991-07-01
申请人： W. Daniel Hillis
发明人： W. Daniel Hillis
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/803 , G06F15/17343
摘要： A parallel computer comprised of a plurality of identical processors, each processor having control and data inputs and outputs for communication with the host computers and separate interprocessor inputs and outputs for communication between the processors. The processors are permanently interconnected through interprocessor communications routers into a first, single n-cube array for purposes of interprocessor communication. The data and control inputs and outputs of the processors are separately connected in parallel to the host computers through a resource allocation means to divide the first, single n-cube array of processors into a multiplicity of smaller second arrays controlled by selected ones of the host computers. All processors of the parallel computer are and remain interconnected into a single boolean n-cube array for interprocessor communication, regardless of the number or identities of the second arrays connected together to a host computer, and each group of one or more second arrays connected to a host computer appear to the host computer as a single array of processors.
摘要翻译：由多个相同的处理器组成的并行计算机，每个处理器具有用于与主计算机进行通信的控制和数据输入和输出以及用于处理器之间的通信的单独的处理器间输入和输出。通过处理器间通信路由器将处理器永久地互连到第一单个n立方体阵列中，以用于处理器间通信。处理器的数据和控制输入和输出通过资源分配装置并行地与主计算机并行地连接，以将处理器的第一单个n维立方体阵列划分成由所选择的主机控制的多个较小的第二阵列电脑。并行计算机的所有处理器并且保持互连成为用于处理器间通信的单个布尔n型立方体数组，而不管连接到主计算机的第二阵列的数量或身份如何，并且每组一个或多个第二阵列连接到主计算机作为单个处理器阵列显示给主机。

86. 发明授权

US5113510A Method and apparatus for operating a cache memory in a multi-processor 失效
标题翻译：用于在多处理器中操作高速缓冲存储器的方法和装置
公开(公告)号：US5113510A
公开(公告)日：1992-05-12
申请号：US136580
申请日：1987-12-22
申请人： W. Daniel Hillis
发明人： W. Daniel Hillis
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： A computer system having a plurality of processors with each processor having associated therewith a cache memory is disclosed. When it becomes necessary for a processor to update its cache with a block of data from main memory, such a block of data is simultaneously loaded into each appropriate cache. Thus, each processor subsequently requiring such updated block of data may retrieve the block from its own cache, and not be required to access main memory.
摘要翻译：公开了具有多个处理器的计算机系统，每个处理器具有与其相关联的高速缓冲存储器。当处理器需要用来自主存储器的数据块更新其高速缓存时，这样的数据块被同时加载到每个适当的高速缓存中。因此，随后要求这种更新的数据块的每个处理器可以从其自己的高速缓存中检索该块，而不需要访问主存储器。

87. 发明授权

US4830376A Puzzles comprised of elements each having a unique arrangement of matchable features 失效
标题翻译：由各自具有独特布置的匹配特征的元件组成的拼图
公开(公告)号：US4830376A
公开(公告)日：1989-05-16
申请号：US142047
申请日：1988-01-07
申请人： W. Daniel Hillis
发明人： W. Daniel Hillis
IPC分类号： A63F9/10 , A63F9/12
CPC分类号： A63F9/12 , A63F9/10
摘要： A two dimensional puzzle is disclosed comprising thirty-six four sided tiles. Each of the tiles includes some means for indicating its orientation; and all but one of the tiles further comprises a part of at least one means for matching the tile to other tiles. The matching means illustratively is an interlocking connector having a male and female element one of which elements is disposed in a side of a first tile and the other of which is disposed in a side of a second tile to which the first tile is connected. Each of the four side surfaces of each tile has either a male connector element, a female connector element or neither element; and each tile has a different combination of these three features on its four sides. The puzzle is to arrange the thirty-six tiles in their correct orientation in a six-by-six rectilinear array so that the tiles interlock. Extensions of the puzzle to other dimensions are also disclosed, in particular, a three-dimensional puzzle of 216 blocks that can be assembled in a six-by-six-by-six array of interlocking blocks.
摘要翻译：公开了一种二维拼图，其包括三十六个四面砖。每个瓦片包括一些用于指示其方向的装置; 并且除了一个瓷砖之外的所有瓷砖还包括至少一个用于将砖与其他砖相匹配的装置的一部分。匹配装置示例性地是具有阳和阴元件的互锁连接器，其中一个元件设置在第一瓦片的侧面，另一个元件设置在第一瓦片连接到第二瓦片的一侧。每个瓦片的四个侧表面中的每一个具有阳连接器元件，阴连接器元件或两个元件; 并且每个瓦片在其四面具有这三个特征的不同组合。拼图是将六十六个瓷砖以正六六位直线阵列排列成正确的方式，以使瓷砖互相联锁。还公开了其他尺寸的拼图的扩展，特别是216个块的三维拼图，其可以以六乘六乘六排的互锁块组装。

88. 发明授权

US4709327A Parallel processor/memory circuit 失效
标题翻译：并行处理器/存储器电路
公开(公告)号：US4709327A
公开(公告)日：1987-11-24
申请号：US499471
申请日：1983-05-31
申请人： W. Daniel Hillis , Thomas F. Knight, Jr. , Alan Bawden , Brewster L. Kahle , David Chapman , David P. Christman , Cliff A. Lasser , Carl R. Feynman
发明人： W. Daniel Hillis , Thomas F. Knight, Jr. , Alan Bawden , Brewster L. Kahle , David Chapman , David P. Christman , Cliff A. Lasser , Carl R. Feynman
IPC分类号： G06F15/80 , G06F15/16
CPC分类号： G06F15/8023
摘要： A parallel processing circuit is disclosed for use as the processor/memory in a highly parallel processor. The circuit comprises an instruction decoder that generates tables of outputs in response to instructions received at the decoder and a plurality of processor/memories each of which comprises a read/write memory and a processor for producing an output depending at least in part on data read from the memory and instruction information received at the instruction decoder. In addition, the circuit provides means for simultaneously addressing at least one cell in each read/write memory to write data thereto or read data therefrom and means for providing to each processor an output table from the decoder, the particular output table depending on instruction information received at the decoder. Further the processing circuit comprises means for selecting from the output table a particular output depending on data input to the processor. Advantageously, each processor/memory also comprises a flag controller for controlling the reading of a plurality of flags and means for simultaneously addressing each flag controller to read a flag for input into the processor associated therewith.Preferably, each processor is a bit-serial processor with three inputs, two from the read/write memory and one from the flag controller, and two outputs, one to the read/write memory and one to the flag controller; and the decoder and the plurality of processor/memories and formed on a single, integrated circuit chip.
摘要翻译：公开了一种用于高度并行处理器中的处理器/存储器的并行处理电路。电路包括指令解码器，其响应于在解码器处接收到的指令而生成输出表，以及多个处理器/存储器，每个处理器/存储器包括读/写存储器和用于至少部分地基于数据读取产生输出的处理器从在指令解码器处接收的存储器和指令信息。此外，电路提供用于同时寻址每个读/写存储器中的至少一个单元以向其中写入数据或从其读取数据的装置，用于向每个处理器提供来自解码器的输出表的装置，该特定输出表取决于指令信息在解码器处接收。此外，处理电路包括用于根据输入到处理器的数据从输出表选择特定输出的装置。有利地，每个处理器/存储器还包括用于控制多个标志的读取的标志控制器和用于同时寻址每个标志控制器以读取用于输入到与其相关联的处理器的标志的装置。优选地，每个处理器是具有三个输入的位串行处理器，两个来自读/写存储器和一个来自标志控制器的两个输出，一个输出到读/写存储器，一个输出到该标志控制器; 以及解码器和多个处理器/存储器并形成在单个集成电路芯片上。

89. 发明授权

US09299274B2 Elements for self assembling displays 有权
公开(公告)号：US09299274B2
公开(公告)日：2016-03-29
申请号：US12215644
申请日：2008-06-27
申请人： W. Daniel Hillis , Nathan P. Myhrvold , Clarence T. Tegreene , Lowell L. Wood, Jr. , Victoria Y. H. Wood
发明人： W. Daniel Hillis , Nathan P. Myhrvold , Clarence T. Tegreene , Lowell L. Wood, Jr. , Victoria Y. H. Wood
IPC分类号： G09G3/34 , G09F9/30 , G09F9/33 , G09G3/00
CPC分类号： G09F9/30 , G09F9/33 , G09G3/001
摘要： Various embodiments of methods and systems for designing and constructing displays from multiple light emitting elements are disclosed. Display elements having different light emitting and self-organizing characteristics may be used during display assembly.

90. 发明授权

US08996486B2 Data store with lock-free stateless paging capability 有权
标题翻译：数据存储，无锁无状态寻呼功能
公开(公告)号：US08996486B2
公开(公告)日：2015-03-31
申请号：US11301985
申请日：2005-12-12
申请人： W. Daniel Hillis , Eric Bax , Augusto Callejas , Harry Kao , Mathias L. Kolehmainen
发明人： W. Daniel Hillis , Eric Bax , Augusto Callejas , Harry Kao , Mathias L. Kolehmainen
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30867 , G06F17/3053 , G06F17/30545 , G06F17/30592 , G06F17/30876
摘要： Disclosed are a method and apparatus for limiting the number of results returned by a data store in response to a query. Upon receiving an initial query, the data store returns a page of results that includes a subset of the data items within the data store satisfying the conditions of the query. The data store also provides a marker indicating the extent of the set of data items. If a subsequent query that requests additional results which satisfy the same query conditions and that includes the marker is received, the data store returns a page of results that includes a subset of data items that are disjoint from the initial subset, and provides an updated marker which indicates the extent of the union of the initial and subsequent subsets. If still further results are desired from the data store, an additional query containing the updated marker may be submitted.
摘要翻译：公开了一种用于限制响应于查询的数据存储返回的结果的数量的方法和装置。在接收到初始查询之后，数据存储返回包含符合查询条件的数据存储库内数据项子集的结果页。数据存储还提供指示数据项集的范围的标记。如果接收到请求满足相同查询条件并且包括标记的附加结果的后续查询，则数据存储返回包括与初始子集不相交的数据项的子集的结果页面，并提供更新的标记这表明初始和后续子集的联合程度。如果从数据存储还需要进一步的结果，则可以提交包含更新的标记的附加查询。

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