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81. 发明授权

US09690619B2 Thread processing method and thread processing system for setting for each thread priority level of access right to access shared memory 有权
公开(公告)号：US09690619B2
公开(公告)日：2017-06-27
申请号：US14057814
申请日：2013-10-18
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara , Toshiya Otomo , Naoki Odate
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50 , G06F9/52
CPC分类号： G06F9/4881 , G06F9/5016 , G06F9/522 , G06F2209/5021
摘要： A thread processing method is executed by a specific apparatus included among a plurality of apparatuses, and includes assigning one thread among a plurality of threads to the apparatuses, respectively; acquiring first time information that indicates a time at which the specific apparatus receives an execution result of a corresponding thread from each of the apparatuses; and setting a priority level of an access right to access shared memory that is shared by the apparatuses and the specific apparatus, the setting being based on the first time information and second time information that indicates a time at which reception of execution results of the threads from the apparatuses ends.

82. 发明授权

US09639905B2 Power control apparatus, electronic computer, and power control method 有权
公开(公告)号：US09639905B2
公开(公告)日：2017-05-02
申请号：US14248874
申请日：2014-04-09
申请人： FUJITSU LIMITED
发明人： Yuta Teranishi , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Toshiya Otomo
IPC分类号： G06Q50/06 , G06F1/32 , G06Q10/06
CPC分类号： G06Q50/06 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06Q10/06 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： A power control apparatus includes a processor configured to collect first information related to operation of a performing unit configured to perform data processing and information related to operation of a bus configured to transfer data; determine an operating frequency and an operating voltage for the performing unit, based on the collected information; estimate based on the collected information, a period elapsing until the performing unit suspends operation and a period elapsing until the bus suspends operation; derive a discriminant that obtains a difference of total power consumption and power consumption pre-switching; and execute a switching of an operating frequency and an operating voltage of the performing unit, based on a value of the discriminant.

83. 发明授权

US09632842B2 Exclusive access control method prohibiting attempt to access a shared resource based on average number of attempts and predetermined threshold 有权
公开(公告)号：US09632842B2
公开(公告)日：2017-04-25
申请号：US14036272
申请日：2013-09-25
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara , Toshiya Otomo , Naoki Odate
IPC分类号： G06F9/52 , G06F12/00
CPC分类号： G06F9/52 , G06F9/526 , G06F12/00
摘要： An exclusive access control method is executed by a computer having an operating system that when an excluded thread accesses a shared resource, executes a first exclusive access control process of prohibiting the excluded thread from attempting to access the shared resource until exclusive access control is released, the exclusive access control process being executed according to a number of attempts, by the excluded thread, to access the shared resources. The exclusive access control method includes counting by at least one second thread, including the excluded thread and different from a first thread, the number of attempts to access the shared resource, when the first thread executes a second exclusive access control process of allowing the excluded thread to attempt to access the shared resource until the excluded thread is permitted access; and storing to a memory area by the second thread, the counted number of attempts.

84. 发明授权

US09622103B2 Communications network control method, computer product, and system 有权
公开(公告)号：US09622103B2
公开(公告)日：2017-04-11
申请号：US15169920
申请日：2016-06-01
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Toshiya Otomo , Hiromasa Yamauchi
IPC分类号： H04W24/10 , H04W16/00 , H04W48/16 , H04W84/18
CPC分类号： H04W24/10 , H04W16/00 , H04W16/18 , H04W48/16 , H04W84/18
摘要： A communications network control method by a computer includes obtaining measurement area information indicating a measurement area of a sensor included in a communications node, the computer obtaining the measurement area information for each communications node in a communications node group that is included in a communications network and that is among plural communications nodes arranged in an arrangement area; obtaining divided area information indicating plural divided areas obtained by dividing the arrangement area; deriving for each divided area among the plural divided areas, a first value corresponding to a count of communications nodes that are in the communications node group and at least partially include the divided area in the measurement area indicated by the obtained measurement area information; and providing control of changing among the plural communications nodes, communications nodes included in the communications network, according to the first value derived for each divided area.

85. 发明授权

US09558152B2 Synchronization method, multi-core processor system, and synchronization system 有权
标题翻译：同步方法，多核处理器系统和同步系统
公开(公告)号：US09558152B2
公开(公告)日：2017-01-31
申请号：US14026469
申请日：2013-09-13
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F9/46 , G06F15/78 , G06F9/52 , G06F9/54 , G06F15/167 , G06F9/45 , G06F9/38 , G06F9/30
CPC分类号： G06F15/7839 , G06F8/458 , G06F9/30087 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3885 , G06F9/467 , G06F9/52 , G06F9/544 , G06F15/167 , G06F2212/507
摘要： A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs.
摘要翻译：同步方法由多核处理器系统执行。同步方法包括基于从第一CPU发出的同步命令，要同步的CPU和CPU的计数到特定表中进行注册; 由每个CPU进行计数，并且基于来自第一CPU的同步信号，同步点的到达计数以及由每个CPU创建作为第一共享存储器区域的复制的第二共享存储区域由CPU执行的进程; 以及当到达计数等于CPU的计数时，比较第一共享存储区域和第二共享存储区域，并且基于比较结果，判断由CPU执行的处理。

86. 发明授权

US09459870B2 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US09459870B2
公开(公告)日：2016-10-04
申请号：US14499334
申请日：2014-09-29
申请人： FUJITSU LIMITED
发明人： Toshiya Otomo , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Yuta Teranishi
IPC分类号： G06F9/30 , G06F9/34 , G06F15/167
CPC分类号： G06F9/30043 , G06F9/30 , G06F9/30036 , G06F9/34 , G06F15/167
摘要： A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers.
摘要翻译：数据处理器包括：处理数据的多个控制器; 程序存储器，分别在多个地址上存储备用指令和数据处理指令; 以及存储多个控制器的不同执行开始地址的队列，其中，在所述多个控制器顺序访问所述队列之后，所述多个控制器以所述顺序访问的顺序从所述队列获取不同的执行开始地址，开始执行来自程序存储器中获取的不同执行开始地址的指令，并且执行数据处理指令并且执行备用指令，以使每个控制器不同的次数。

87. 发明授权

US09448931B2 Endian conversion method and system 有权
标题翻译： Endian转换方法和系统
公开(公告)号：US09448931B2
公开(公告)日：2016-09-20
申请号：US14029425
申请日：2013-09-17
申请人： FUJITSU LIMITED
发明人： Akihito Kataoka , Koichiro Yamashita , Naoki Odate , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Toshiya Otomo
IPC分类号： G06F13/10 , G06F12/06 , G06F7/76
CPC分类号： G06F12/06 , G06F7/768 , G06F2213/0038
摘要： An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory.
摘要翻译：一个字节序转换方法由CPU执行，并且包括执行一个包括字节序转换设置的程序; 并且当访问在所述末端转换设置中指示的主存储器的地址时，执行由所述主存储器的地址指定的数据的末端转换。

88. 发明授权

US09430388B2 Scheduler, multi-core processor system, and scheduling method 有权
公开(公告)号：US09430388B2
公开(公告)日：2016-08-30
申请号：US14601978
申请日：2015-01-21
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F12/08 , G06F9/48 , G06F9/54 , B29C49/06 , B29C49/42 , B29D22/00 , B29C49/18 , B29C49/64
CPC分类号： G06F12/0811 , B29C49/062 , B29C49/18 , B29C49/4215 , B29C49/6427 , B29D22/003 , G06F9/544 , G06F12/0875 , G06F12/0888 , G06F2212/283
摘要： A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

89. 发明授权

US09367459B2 Scheduling method and multi-core processor system 有权
标题翻译：调度方法和多核处理器系统
公开(公告)号：US09367459B2
公开(公告)日：2016-06-14
申请号：US13934951
申请日：2013-07-03
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F9/38 , G06F12/08 , G06F9/48 , G06F3/06 , G06F12/02 , G06F9/50
CPC分类号： G06F12/0815 , G06F3/065 , G06F9/3851 , G06F9/4843 , G06F9/5016 , G06F12/0284 , Y02D10/13 , Y02D10/22
摘要： A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area.
摘要翻译：管理线程的调度器的调度方法由计算机执行。调度方法包括当从要处理的第一线程生成第二线程时，选择相对较小负载的CPU; 确定所述第二线程是否仅从所述第一线程操作; 当第二线程专门操作时，将由第一线程评估的第一存储区域复制到由CPU管理的第二存储区域上; 基于第二存储区域的地址和预定值计算第二线程的访问第一存储区域的第二地址的偏移量; 并向CPU通知第二地址的偏移量，以将第一地址转换为用于访问第二存储区域的第三地址。

90. 发明申请

US20160112280A1 DATA NETWORK MANAGEMENT SYSTEM, DATA NETWORK MANAGEMENT APPARATUS, DATA PROCESSING APPARATUS, AND DATA NETWORK MANAGEMENT METHOD 审中-公开
标题翻译：数据网络管理系统，数据网络管理设备，数据处理设备和数据网络管理方法
公开(公告)号：US20160112280A1
公开(公告)日：2016-04-21
申请号：US14979417
申请日：2015-12-27
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Toshiya Otomo
IPC分类号： H04L12/24
CPC分类号： H04L41/32 , H04L41/085 , H04L41/28 , H04W24/02
摘要： A data network management system includes a data network management apparatus; and plural data processing apparatuses installed in an installation area and configured to transmit data to the data network management apparatus. The plural data processing apparatuses transmit identification information thereof together with the processed data to the data network management apparatus. The data network management apparatus determines based on identification information of data processing apparatuses that have completed a given authentication test among the plural data processing apparatuses and the identification information obtained from the plural data processing apparatuses installed in the installation area, a first data processing apparatus from which the data is to be obtained among the plural data processing apparatuses.
摘要翻译：数据网络管理系统包括数据网络管理装置; 以及多个数据处理装置，安装在安装区域并被配置为向数据网络管理装置发送数据。多个数据处理装置将其处理后的数据的识别信息与数据网络管理装置进行通信。数据网络管理装置根据在多个数据处理装置中完成了给定认证测试的数据处理装置的识别信息和从安装在安装区域的多个数据处理装置获得的识别信息，确定第一数据处理装置，在多个数据处理装置中获得数据。

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