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81. 发明授权

US09601385B1 Method of making a dual strained channel semiconductor device 有权
公开(公告)号：US09601385B1
公开(公告)日：2017-03-21
申请号：US15007970
申请日：2016-01-27
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L29/78 , H01L29/772 , H01L27/12 , H01L21/8238 , H01L21/033 , H01L29/161 , H01L29/165 , H01L29/66
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming a semiconductor device includes forming on a substrate mandrels made from a semiconductor material. A semiconductor material having a lattice constant that is different than the mandrel semiconductor material is deposited onto sidewalls of the mandrels to form strained semiconductor layers. The mandrels are at least partially removed to form free-standing or partially-supported fins that include the strained semiconductor layers. The strained semiconductor layers may include tensile silicon or compressive silicon germanium, which can be used to form a dual strained channel semiconductor device.

82. 发明授权

US09590057B2 Reduced parasitic capacitance with slotted contact 有权
标题翻译：降低寄生电容与开槽接触
公开(公告)号：US09590057B2
公开(公告)日：2017-03-07
申请号：US14242909
申请日：2014-04-02
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L29/417 , H01L29/78 , H01L29/66
CPC分类号： H01L29/41758 , H01L29/41775 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/7851
摘要： A FET device fabricated by providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate. A second conductor is provided adjacent the first conductor, the second conductor having a second top surface with a second height above the substrate. A portion of the second conductor is removed to provide a slot, wherein the slot is defined by opposing interior sidewalls and a bottom portion, such that the bottom portion of the slot is below the first height of the first conductor. An insulating material is deposited in the slot, the insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide space within the slot for a third conductor. The space within the slot is then filled with the third conductor.
摘要翻译：通过在衬底上设置第一导体而制造的FET器件，所述第一导体具有在衬底上方具有第一高度的第一顶表面。第二导体设置成与第一导体相邻，第二导体具有在衬底上方具有第二高度的第二顶表面。去除第二导体的一部分以提供狭槽，其中狭槽由相对的内侧壁和底部限定，使得槽的底部部分低于第一导体的第一高度。绝缘材料沉积在槽中，绝缘材料具有在基板上方具有第三高度的第三顶表面，第三高度低于第二导体的第二高度，以在第三导体的槽内提供空间。然后用第三导体填充槽内的空间。

83. 发明申请

US20170040319A1 SELF-CUT SIDEWALL IMAGE TRANSFER PROCESS 审中-公开
标题翻译：自动切割面板图像传输过程
公开(公告)号：US20170040319A1
公开(公告)日：2017-02-09
申请号：US15331074
申请日：2016-10-21
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L27/088 , H01L21/308 , H01L21/8234 , H01L21/3213 , H01L29/78 , H01L21/033 , H01L21/311
摘要： A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask.
摘要翻译：在硅衬底上形成多个心轴。心轴以给定的间距间隔开，其中形成具有第一宽度的多个心轴中的至少一个，并且形成具有第二宽度的多个心轴中的至少另一个，并且其中第一宽度更大比第二个宽度。通过在侧壁图像转印过程中去除多个心轴的至少一部分而不使用切割掩模来形成至少一个结构。

84. 发明申请

US20170033223A1 AIR GAP CONTACT FORMATION FOR REDUCING PARASITIC CAPACITANCE 有权
公开(公告)号：US20170033223A1
公开(公告)日：2017-02-02
申请号：US15294391
申请日：2016-10-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Effendi Leobandung
IPC分类号： H01L29/78 , H01L23/535 , H01L29/08 , H01L21/768
CPC分类号： H01L29/66795 , H01L21/30604 , H01L21/764 , H01L21/7682 , H01L21/76895 , H01L21/76897 , H01L23/5222 , H01L23/535 , H01L29/0847 , H01L29/42368 , H01L29/4238 , H01L29/7851 , H01L2221/1063
摘要： A functional gate structure is located on a surface of a semiconductor material portion and including a U-shaped gate dielectric portion and a gate conductor portion. A source region is located on one side of the functional gate structure, and a drain region is located on another side of the functional gate structure. The source region and drain region both have a topmost surface that is above a topmost surface of the semiconductor material portion and another surface that touches a portion of the U-shaped gate dielectric. A contact structure is located on the topmost surface of the source region and/or the drain region. A middle-of-the-line air gap contact is located between the contact structure and the functional gate structure and above at least one of the source region and the drain region. The middle-of-the-line air gap contact is sealed by a portion of a conformal dielectric material.

85. 发明授权

US09548358B2 Dual fill silicon-on-nothing field effect transistor 有权
标题翻译：双重填充无硅无源场效应晶体管
公开(公告)号：US09548358B2
公开(公告)日：2017-01-17
申请号：US14280777
申请日：2014-05-19
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66
CPC分类号： H01L29/66742 , H01L21/02532 , H01L21/02603 , H01L29/0669 , H01L29/0673 , H01L29/42392 , H01L29/66 , H01L29/66545 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/78603 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a substrate. After formation of a first dielectric isolation layer around the patterned stack, a disposable gate structure can be formed. End portions of the second silicon-germanium alloy nanowire are removed to form first cavities underlying end portions of the silicon-containing nanowire. Dielectric nanowires are formed in cavities concurrently with formation of a gate spacer. After recessing the first dielectric isolation layer, a second cavity is formed by removing the first silicon-germanium alloy nanowire. The second cavity is filled with a second dielectric isolation layer, and raised active regions can be formed by a selective epitaxy process. After formation of a planarization dielectric layer, the disposable gate structure and the remaining portion of the second silicon-germanium alloy nanowire with a replacement gate structure.
摘要翻译：在基板上形成第一硅 - 锗合金纳米线，第二硅 - 锗合金纳米线和含硅纳米线的图案化叠层。在图案化堆叠周围形成第一介电隔离层之后，可以形成一次性栅极结构。去除第二硅 - 锗合金纳米线的端部以形成位于含硅纳米线的端部下方的第一空腔。电介质纳米线与形成栅极间隔物同时形成。在凹陷第一介电隔离层之后，通过去除第一硅 - 锗合金纳米线形成第二空腔。第二腔填充有第二介电隔离层，并且可以通过选择性外延工艺形成凸起的有源区。在形成平坦化电介质层之后，一次性栅极结构和具有置换栅极结构的第二硅 - 锗合金纳米线的剩余部分。

86. 发明授权

US09536832B1 Junctionless back end of the line via contact 有权
标题翻译：通过接触线路的无功后端
公开(公告)号：US09536832B1
公开(公告)日：2017-01-03
申请号：US14983643
申请日：2015-12-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Effendi Leobandung
IPC分类号： H01L21/4763 , H01L23/528 , H01L21/768 , H01L21/3213 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5283 , H01L21/32134 , H01L21/76804 , H01L21/76805 , H01L21/76844 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295
摘要： A method of forming an interconnect structure includes providing a first dielectric layer, patterning a wire opening in a first dielectric layer, lining the wire opening with a metal liner and includes filling the wire opening with a first conductive material. The method also includes depositing a first cap on the first dielectric layer, depositing a second dielectric layer, and patterning a via trench in the second dielectric layer. The method also includes depositing a metal liner, removing the metal liner from a via junction, and enlarging the contact area. The method also includes filling the via trench with a second conductive material to form a via.
摘要翻译：形成互连结构的方法包括提供第一介电层，图案化第一电介质层中的电线开口，用金属衬垫衬套电线开口，并且包括用第一导电材料填充电线开口。该方法还包括在第一电介质层上沉积第一帽，沉积第二电介质层，以及在第二电介质层中构图通孔沟槽。该方法还包括沉积金属衬垫，从通孔接头移除金属衬垫，并扩大接触面积。该方法还包括用第二导电材料填充通孔，以形成通孔。

87. 发明申请

US20160380001A1 SELECTIVE OXIDATION FOR MAKING RELAXED SILICON GERMANIUM ON INSULATOR STRUCTURES 有权
标题翻译：选择性氧化制备绝缘硅结构上的松散硅
公开(公告)号：US20160380001A1
公开(公告)日：2016-12-29
申请号：US14750485
申请日：2015-06-25
申请人： International Business Machines Corporation
发明人： Stephen W. Bedell , Effendi Leobandung , Devendra K. Sadana , Min Yang
IPC分类号： H01L27/12 , H01L29/06 , H01L29/161 , H01L29/78 , H01L29/66
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/0649 , H01L29/1054 , H01L29/161 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Methods and devices are provided to fabricate semiconductor devices with, e.g., SiGe-on-insulator structures. For example, a method for fabricating a semiconductor device includes forming a crystalline buffer layer on a substrate, forming an epitaxial semiconductor layer on the crystalline buffer layer, patterning the epitaxial semiconductor layer to form a patterned epitaxial semiconductor layer, and oxidizing a surface region of the crystalline buffer layer selective to the patterned epitaxial semiconductor layer to convert the surface region of the crystalline buffer layer to an insulating layer. The insulating layer insulates the patterned epitaxial semiconductor layer from the crystalline buffer layer. In one example structure, the substrate is a silicon substrate, the crystalline buffer layer is formed of germanium, the epitaxial semiconductor layer is formed of silicon-germanium, and the insulating layer is formed of amorphous germanium-oxide.
摘要翻译：提供了用于制造具有例如绝缘体上硅结构的半导体器件的方法和装置。例如，制造半导体器件的方法包括在衬底上形成晶体缓冲层，在晶体缓冲层上形成外延半导体层，图案化外延半导体层以形成图案化外延半导体层，并氧化表面区域对图案化的外延半导体层选择性地将结晶缓冲层的表面区域转换成绝缘层的结晶缓冲层。绝缘层将图案化的外延半导体层与晶体缓冲层绝缘。在一个示例性结构中，衬底是硅衬底，晶体缓冲层由锗形成，外延半导体层由硅 - 锗形成，绝缘层由无定形锗氧化物形成。

88. 发明授权

US09530665B2 Protective trench layer and gate spacer in finFET devices 有权
标题翻译： finFET器件中的保护沟槽层和栅极间隔
公开(公告)号：US09530665B2
公开(公告)日：2016-12-27
申请号：US14313340
申请日：2014-06-24
申请人： International Business Machines Corporation
发明人： Effendi Leobandung , Richard S. Wise
IPC分类号： H01L21/311 , H01L29/66 , H01L21/8238 , H01L27/092 , H01L27/088 , H01L27/12 , H01L21/8234
CPC分类号： H01L21/31116 , H01L21/31105 , H01L21/823431 , H01L21/823468 , H01L21/823821 , H01L21/823864 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/66795
摘要： Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer.
摘要翻译：形成场效应晶体管器件包括在半导体衬底上形成第一和第二半导体鳍片。第一和第二半导体散热片被沟槽区分开。沟槽区域具有对应于第一半导体鳍片的侧壁的第一侧壁和对应于第二半导体鳍片的侧壁的第二侧壁。栅极堆叠被布置在第一和半导体鳍片的相应沟道区域上。栅堆叠的第一侧壁对应于沟槽区域的第三侧壁。仅在沟槽区域的底部和栅极叠层的第一侧壁上形成保护层。沿着栅极堆叠的第一侧壁的保护层限定栅极间隔物。

89. 发明申请

US20160372471A1 INTEGRATED CIRCUIT HAVING DUAL MATERIAL CMOS INTEGRATION AND METHOD TO FABRICATE SAME 有权
标题翻译：具有双重材料CMOS集成的集成电路及其制造方法
公开(公告)号：US20160372471A1
公开(公告)日：2016-12-22
申请号：US14997773
申请日：2016-01-18
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L27/092 , H01L21/84 , H01L29/20 , H01L21/8238 , H01L21/324 , H01L29/16 , H01L27/12 , H01L29/06
CPC分类号： H01L27/0924 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823864 , H01L21/8258 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/517 , H01L29/66469 , H01L29/66545 , H01L29/6656 , H01L29/775 , H01L29/7848
摘要： In one aspect thereof the invention provides a structure that includes a substrate having a surface and a plurality of fins supported by the surface of the substrate. The plurality of fins are formed of Group IVA-based crystalline semiconductor material and are spaced apart and generally parallel to one another. In the structure at least some of the plurality of fins comprise an amorphous region forming a nanowire precursor structure that is located along a length of the fin where a Group III-V transistor is to be located. A method to fabricate the structure and other structures is also disclosed.
摘要翻译：在其一个方面，本发明提供一种结构，其包括具有表面的基板和由基板的表面支撑的多个翅片。多个翅片由基于IVA的晶体半导体材料形成并且彼此间隔开并且大体上彼此平行。在该结构中，多个翅片中的至少一些鳍片包括形成纳米线前体结构的非晶区域，其沿着鳍III的长度设置，其中III-V晶体管将被定位。还公开了制造结构和其它结构的方法。

90. 发明申请

US20160365287A1 SELF-ALIGNED HARD MASK FOR EPITAXY PROTECTION 有权
标题翻译：自对准的外壳防护面罩
公开(公告)号：US20160365287A1
公开(公告)日：2016-12-15
申请号：US14734538
申请日：2015-06-09
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L21/8238 , H01L21/762 , H01L21/311 , H01L21/3065 , H01L29/06 , H01L21/02 , H01L29/417 , H01L27/092 , H01L27/108 , H01L29/66 , H01L21/308
CPC分类号： H01L21/823814 , H01L21/76224 , H01L21/823878 , H01L27/092 , H01L29/0649 , H01L29/41783 , H01L29/6653 , H01L29/66636
摘要： A method includes isolating a first and at least a second region on a semiconductor substrate, and forming one or more devices on each of the first and at least second regions. Forming the one or more devices includes forming at least one gate structures in each of the first and at least second regions on a first surface of the substrate, depositing a spacer over the gate structures in each of the first and the at least second regions and over the first surface of the substrate, etching horizontal portions of the spacer in the first region, growing epitaxial portions in the first region in alignment with said at least one gate structure in the first region, oxidizing exposed surfaces of the epitaxial portions in the first region, and repeating the etching, growing and oxidizing steps for the at least second region.
摘要翻译：一种方法包括隔离半导体衬底上的第一和至少第二区域，以及在第一和至少第二区域中的每一个上形成一个或多个器件。形成所述一个或多个器件包括在所述衬底的第一表面上的所述第一和至少第二区域中的每一个中形成至少一个栅极结构，在所述第一区域和所述至少第二区域中的每个区域中的所述栅极结构上方沉积间隔物，以及在衬底的第一表面上蚀刻第一区域中的间隔物的水平部分，在第一区域中生长外延部分与第一区域中的所述至少一个栅极结构对准，将第一区域中的外延部分的暴露表面氧化并且重复所述至少第二区域的蚀刻，生长和氧化步骤。

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