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81. 发明授权

US09455135B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09455135B2
公开(公告)日：2016-09-27
申请号：US14562768
申请日：2014-12-07
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Feng-Yi Chang , En-Chiuan Liou , Chieh-Te Chen
IPC分类号： H01L21/302 , H01L21/02 , H01L21/311 , H01L21/033 , H01L21/027
CPC分类号： H01L21/0206 , H01L21/02186 , H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/31138 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成硬掩模; 在硬掩模上形成第一图案化掩模层; 使用第一图案化掩模层去除用于形成图案化硬掩模的硬掩模的一部分; 并且利用气体剥离第一图案化掩模层，同时在图案化的硬掩模上形成保护层，其中气体选自N2和O2。

82. 发明申请

US20160268203A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160268203A1
公开(公告)日：2016-09-15
申请号：US14681119
申请日：2015-04-08
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Feng-Yi Chang , Chih-Sen Huang , Ching-Wen Hung , Wei-Hao Huang
IPC分类号： H01L23/535 , H01L29/78 , H01L21/768 , H01L21/3115 , H01L21/311
CPC分类号： H01L29/78 , H01L21/31144 , H01L21/3115 , H01L21/31155 , H01L21/76825 , H01L21/76897 , H01L29/66545
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层，其中栅极结构包括其上的硬掩模; 在栅极结构和ILD层上形成介电层; 去除介电层的一部分以暴露硬掩模和ILD层; 并进行表面处理以在硬掩模和ILD层中形成掺杂区域。

83. 发明授权

US09349812B2 Semiconductor device with self-aligned contact and method of manufacturing the same 有权
标题翻译：具有自对准接触的半导体器件及其制造方法
公开(公告)号：US09349812B2
公开(公告)日：2016-05-24
申请号：US13902975
申请日：2013-05-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chieh-Te Chen , Feng-Yi Chang , Hsuan-Hsu Chen
IPC分类号： H01L29/417 , H01L29/06 , H01L21/311 , H01L21/768 , H01L23/485 , H01L29/66
CPC分类号： H01L29/41775 , H01L21/31144 , H01L21/76816 , H01L21/76897 , H01L23/485 , H01L29/0692 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in the self-aligned contact trench; patterning the 2nd dielectric layer into a 1st portion on the 1st dielectric layer and a 2nd portion filling in the self-aligned contact trench, using the 2nd dielectric layer as a mask to etch the 1st dielectric layer, and forming a metal layer and a self-aligned contact simultaneously in the 1st dielectric layer and in the self-aligned contact trench.
摘要翻译：具有自对准接触的半导体器件及其制造方法，其中所述方法包括在栅极结构上形成第一介电层的步骤，在两个栅极结构之间形成自对准接触沟槽，形成第二介电层在第一电介质层和自对准接触沟槽中; 将第二电介质层图案化为第一介电层上的第一部分，并且使用第二介电层作为掩模来蚀刻第一介电层，并形成金属层和自身的第二部分填充在自对准接触沟槽中在第一电介质层和自对准接触沟槽中同时进行。

84. 发明申请

US20160104645A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160104645A1
公开(公告)日：2016-04-14
申请号：US14536696
申请日：2014-11-10
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Wen Hung , Chih-Sen Huang , Yi-Wei Chen , Chien-Ting Lin , Shih-Fang Tzou , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Feng-Yi Chang , Chieh-Te Chen
IPC分类号： H01L21/8234 , H01L21/311 , H01L29/49 , H01L29/06 , H01L27/088 , H01L21/02 , H01L21/768
CPC分类号： H01L21/823437 , H01L21/31144 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L27/088 , H01L27/0886 , H01L29/0653 , H01L29/495 , H01L29/4966
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供衬底; 在所述基板上形成多个栅极结构; 在栅极结构上形成第一阻挡层; 在所述第一停止层上形成第二停止层; 在所述第二停止层上形成第一电介质层; 在所述第一电介质层中形成多个第一开口以露出所述第二阻挡层; 在所述第一介电层和所述第二停止层中形成多个第二开口以暴露所述第一停止层; 以及去除所述第二停止层的一部分和所述第一停止层的一部分以暴露所述栅极结构。

85. 发明申请

US20150325453A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20150325453A1
公开(公告)日：2015-11-12
申请号：US14273283
申请日：2014-05-08
申请人： United Microelectronics Corp.
发明人： Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Feng-Yi Chang , Chieh-Te Chen , Cheng-Hsing Chuang
IPC分类号： H01L21/311
CPC分类号： H01L21/31111 , H01L21/31133 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.
摘要翻译：提供一种形成半导体器件的方法。在基板上依次形成材料层，第一流动材料层和第一掩模层。通过使用第一掩模层作为掩模来进行第一蚀刻工艺，以在材料层中形成第一开口。去除第一掩模层和第一流动材料层。在第一开口中形成填充层。在材料层和填料层上形成第二流动材料层。在第二流动材料层上形成第二掩模层。通过使用第二掩模层作为掩模来进行第二蚀刻处理，以在材料层中形成第二开口。

86. 发明授权

US08993433B2 Manufacturing method for forming a self aligned contact 有权
标题翻译：用于形成自对准接触的制造方法
公开(公告)号：US08993433B2
公开(公告)日：2015-03-31
申请号：US13902977
申请日：2013-05-27
申请人： United Microelectronics Corp.
发明人： Chieh-Te Chen , Yu-Tsung Lai , Hsuan-Hsu Chen , Feng-Yi Chang , Chih-Sen Huang , Ching-Wen Hung
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/76843 , H01L21/76895 , H01L21/76897 , H01L23/485
摘要： The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.
摘要翻译：本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极，至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露部分金属栅极并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。

87. 发明申请

US20140342553A1 Method for Forming Semiconductor Structure Having Opening 审中-公开
标题翻译：形成具有开口的半导体结构的方法
公开(公告)号：US20140342553A1
公开(公告)日：2014-11-20
申请号：US13893349
申请日：2013-05-14
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chieh-Te Chen , Feng-Yi Chang , Hsuan-Hsu Chen , Yu-Tsung Lai , Chih-Sen Huang , Ching-Wen Hung
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/31144 , H01L21/76816
摘要： According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.
摘要翻译：根据本发明的一个实施例，提供一种形成具有开口的半导体结构的方法。首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。然后，在基板上形成材料层。第一硬掩模和第二硬掩模形成在材料层上。第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。

88. 发明申请

US20210242214A1 CONTACTS AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20210242214A1
公开(公告)日：2021-08-05
申请号：US17235950
申请日：2021-04-21
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Feng-Yi Chang , Fu-Che Lee
IPC分类号： H01L27/108
摘要： A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

89. 发明申请

US20210242013A1 PATTERNED STRUCTURE 有权
公开(公告)号：US20210242013A1
公开(公告)日：2021-08-05
申请号：US17234818
申请日：2021-04-20
申请人： United Microelectronics Corp. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Feng-Yi Chang , Fu-Che Lee
IPC分类号： H01L21/027 , H01L21/311 , H01L21/768 , H01L21/033
摘要： A patterning method includes the following steps. A mask layer is formed on a material layer. A first hole is formed in the mask layer by a first photolithography process. A first mask pattern is formed in the first hole. A second hole is formed in the mask layer by a second photolithography process. A first spacer is formed on an inner wall of the second hole. A second mask pattern is formed in the second hole after the step of forming the first spacer. The first spacer surrounds the second mask pattern in the second hole. The mask layer and the first spacer are removed. The pattern of the first mask pattern and the second mask pattern are transferred to the material layer by an etching process.

90. 发明授权

US11038014B2 Semiconductor device having plug and metal line 有权
公开(公告)号：US11038014B2
公开(公告)日：2021-06-15
申请号：US16154704
申请日：2018-10-08
申请人： UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
发明人： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC分类号： H01L29/76 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
摘要： A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

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