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81. 发明授权

US07375019B2 Image sensor and method for fabricating the same 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US07375019B2
公开(公告)日：2008-05-20
申请号：US11022645
申请日：2004-12-28
申请人： Hee Sung Shim
发明人： Hee Sung Shim
IPC分类号： H01L21/44
CPC分类号： H01L27/14689 , H01L21/28525 , H01L21/76814 , H01L27/14609 , H01L27/14636 , H01L27/14643 , H01L27/14687
摘要： An image sensor and a method for fabricating the same are disclosed, to improve a contact quality between a contact plug and a source diffusion layer. The image sensor includes a photodiode in an active area of a semiconductor substrate, for receiving incident external light and generating optical charges; a transistor having an impurity diffusion layer electrically connected with the photodiode, for transferring/discharging the optical charges generated by the photodiode to a signal processing circuit; an impurity implantation layer having impurity selectively implanted thereto, for selectively covering the impurity diffusion layer; an insulating interlayer above the semiconductor substrate to cover the photodiode, the transistor, and the impurity implantation layer; an open hole penetrating the insulating interlayer, for selectively opening the impurity diffusion layer; and a contact plug for filling the open hole, and electrically connecting the impurity diffusion layer and a metal line provided above the insulating interlayer.
摘要翻译：公开了一种图像传感器及其制造方法，以改善接触插塞和源极扩散层之间的接触质量。图像传感器包括在半导体衬底的有效区域中的光电二极管，用于接收入射的外部光并产生光电荷; 具有与光电二极管电连接的杂质扩散层的晶体管，用于将由光电二极管产生的光电荷传送/放电到信号处理电路; 具有选择性地注入杂质的杂质注入层，用于选择性地覆盖杂质扩散层; 在半导体衬底上方的绝缘中间层，以覆盖光电二极管，晶体管和杂质注入层; 穿透绝缘中间层的开孔，用于选择性地打开杂质扩散层; 以及用于填充开孔的接触插塞，并且电连接杂质扩散层和设置在绝缘中间层上方的金属线。

82. 发明授权

US07374999B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07374999B2
公开(公告)日：2008-05-20
申请号：US11318441
申请日：2005-12-28
申请人： Kwang Young Ko
发明人： Kwang Young Ko
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/76202 , H01L21/76224 , H01L21/823481 , H01L27/088 , H01L29/0653 , H01L29/42368 , H01L29/7835
摘要： A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-voltage transistor area; and a shallow-trench isolation layer provided as a device isolation layer of the low-voltage transistor area. Accordingly, a sufficient breakdown voltage level can be provided in a high-voltage transistor area, on-resistance and leakage current can be enhanced, and the chip area in a low-voltage transistor area can be reduced.
摘要翻译：半导体器件包括：衬底，其包括设置有高压晶体管的高压晶体管区域和设置有低压晶体管的低压晶体管区域; 提供作为高压晶体管区域的器件隔离层的LOCOS层; 以及作为低压晶体管区域的器件隔离层提供的浅沟槽隔离层。因此，可以在高压晶体管区域提供足够的击穿电压电平，可以提高导通电阻和漏电流，并且可以降低低压晶体管区域中的芯片面积。

83. 发明授权

US07374967B2 Multi-stack chip size packaging method 失效
标题翻译：多堆芯片尺寸封装方法
公开(公告)号：US07374967B2
公开(公告)日：2008-05-20
申请号：US10747108
申请日：2003-12-30
申请人： Naewon Lee
发明人： Naewon Lee
IPC分类号： H01L21/00
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/4334 , H01L25/0657 , H01L2224/16 , H01L2224/32145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06517 , H01L2225/06582 , H01L2225/06589 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.
摘要翻译：在多堆芯片尺寸封装多个芯片中，第一芯片使用凸块在衬底的顶表面上电互连。接下来，在第一芯片上涂覆环氧树脂，并在其上层叠第二芯片，其中第二芯片通过内部引线键合与基板电连接。将灌封溶液涂覆在基材和第二芯片上，并在其上安装散热器，然后固化。封装树脂涂覆在基板的底表面上，并通过凸块和内引线凸块将第三芯片电连接到基板的底表面。

84. 发明授权

US07371679B2 Semiconductor device with a metal line and method of forming the same 失效
标题翻译：具有金属线的半导体器件及其形成方法
公开(公告)号：US07371679B2
公开(公告)日：2008-05-13
申请号：US11320397
申请日：2005-12-29
申请人： Sung-Ho Jang
发明人： Sung-Ho Jang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/7684 , H01L21/76888
摘要： A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on the planarized substrate. The method further includes depositing a barrier metal layer in the via hole, filling a refractory metal in an upper part of the barrier metal layer, planarizing the substrate filled with the refractory metal by performing a second CMP process, forming a refractory metal oxide layer by oxidizing a residual refractory metal region created by the second CMP process, and forming a refractory metal plug by removing the refractory metal oxide layer through a third CMP process.
摘要翻译：一种在半导体器件中形成金属线的方法，包括在包括预定图案的半导体衬底上形成金属间电介质（IMD）层，通过第一CMP工艺对IMD层进行平坦化，并且在平坦化衬底上图形化通孔。该方法还包括在通孔中沉积阻挡金属层，在阻挡金属层的上部填充难熔金属，通过进行第二CMP工艺平坦化填充有难熔金属的衬底，通过第二CMP工艺形成难熔金属氧化物层氧化由第二CMP工艺产生的残余难熔金属区域，以及通过第三CMP工艺去除难熔金属氧化物层来形成耐火金属插塞。

85. 发明授权

US07365347B2 Ion implantation apparatus for use in manufacturing of semiconductor device 失效
标题翻译：用于制造半导体器件的离子注入装置
公开(公告)号：US07365347B2
公开(公告)日：2008-04-29
申请号：US11166679
申请日：2005-06-23
申请人： Jin Ha Park
发明人： Jin Ha Park
IPC分类号： G01K1/08 , H01J3/14 , H01J3/26
CPC分类号： H01J37/3023 , H01J2237/30411 , H01J2237/31701
摘要： Disclosed herein is an ion implantation apparatus for use in manufacturing of a semiconductor device, which has a software program including an option for selecting a manipulator, enabling a time for beam tuning to be minimized. The ion implantation apparatus further includes a manipulator for extracting and focusing an ion source and an ion beam, a control block for controlling overall operation of the ion implantation apparatus and recognizing a newly installed manipulator, and a control window on which a selection menu is displayed, allowing recipe data to be selected on a screen. When installing a replacement manipulator, recipe data for the replacement manipulator can be selected to improve beam tuning set up time.
摘要翻译：本文公开了一种用于制造半导体器件的离子注入装置，其具有包括用于选择操纵器的选项的软件程序，使得能够使波束调谐的时间最小化。离子注入装置还包括用于提取和聚焦离子源和离子束的操纵器，用于控制离子注入装置的总体操作并识别新安装的操纵器的控制块以及显示选择菜单的控制窗口，允许在屏幕上选择食谱数据。当安装更换机械手时，可以选择更换机械手的配方数据，以改善梁的调整设置时间。

86. 发明授权

US07358595B2 Method for manufacturing MOS transistor 失效
标题翻译：制造MOS晶体管的方法
公开(公告)号：US07358595B2
公开(公告)日：2008-04-15
申请号：US11483143
申请日：2006-07-07
申请人： Eun Jong Shin
发明人： Eun Jong Shin
IPC分类号： H01L23/58 , H01L21/302 , H01L21/461
CPC分类号： H01L29/7843 , H01L29/6656 , H01L29/66583
摘要： Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD region in the substrate under the buffer pattern; forming a spacer on a top surface of the buffer pattern and sidewalls of the gate electrode; and forming a source/drain region in the substrate under the buffer pattern.
摘要翻译：公开了一种用于制造MOS晶体管的方法。本方法包括在半导体衬底上形成包括氮的缓冲层图案; 在暴露的基板表面上形成栅极绝缘层和栅电极; 在缓冲图案下在衬底中形成LDD区; 在缓冲图案的顶表面和栅电极的侧壁上形成间隔物; 以及在所述衬底中在所述缓冲图案下形成源/漏区。

87. 发明授权

US07358575B2 Method of fabricating SRAM device 失效
标题翻译：制造SRAM器件的方法
公开(公告)号：US07358575B2
公开(公告)日：2008-04-15
申请号：US11603886
申请日：2006-11-21
申请人： Tae Woo Kim
发明人： Tae Woo Kim
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11 , Y10S257/903
摘要： A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on a periphery area of the semiconductor substrate, stacking first to third insulating layers over the substrate, forming a spacer on a sidewall of the third conductor pattern in the exposed periphery area, removing the third insulating layer, and forming first and second spacers on sidewalls of the first and second conductor patterns.
摘要翻译：提供一种制造SRAM器件的方法，通过该方法，结节点区域稳定地固定在1T型SRAM器件中。该方法包括在半导体衬底的单元区域上形成第一和第二导体图案以及在半导体衬底的周边区域上的第三导体图案，在衬底上堆叠第一至第三绝缘层，在第三层的侧壁上形成间隔物导体图案，去除第三绝缘层，以及在第一和第二导体图案的侧壁上形成第一和第二间隔物。

88. 发明授权

US07358128B2 Method for manufacturing a transistor 失效
标题翻译：制造晶体管的方法
公开(公告)号：US07358128B2
公开(公告)日：2008-04-15
申请号：US11121499
申请日：2005-05-03
申请人： Jea Hee Kim
发明人： Jea Hee Kim
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L29/4966 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semiconductor device includes a semiconductor substrate; a gate insulating layer and a gate electrode on the semiconductor substrate; spacers at sidewalls of the gate electrode, wherein the spacer contains nitrogen to obtain or increase its tensile stress; and source and drain regions in the semiconductor substrate adjacent to the gate electrode.
摘要翻译：公开了一种半导体器件及其制造方法，其中包含氮的间隔物具有拉伸应力，并且通过不考虑晶体管的种类来改善导通电流而使器件可靠性得到改善。半导体器件包括半导体衬底; 半导体衬底上的栅极绝缘层和栅电极; 间隔物在栅电极的侧壁处，其中间隔物含有氮以获得或增加其拉伸应力; 以及与栅极相邻的半导体衬底中的源极和漏极区域。

89. 发明授权

US07355243B2 Flash memory device and method for fabricating the same 失效
标题翻译：闪存装置及其制造方法
公开(公告)号：US07355243B2
公开(公告)日：2008-04-08
申请号：US11320862
申请日：2005-12-30
申请人： Sang Woo Nam
发明人： Sang Woo Nam
IPC分类号： H01L29/788
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region and the isolation layer, and a sidewall spacer is formed at sidewalls of the gate stack. The device further includes a common source line that electrically interconnects a plurality of sources of a plurality of the flash memory cells, and is formed in the isolation layer by removing an insulating material in the isolation layer and is formed in parallel to a word line formed over the gate stack. A silicide layer is formed in the common source line.
摘要翻译：一种闪存器件，包括用于限定半导体衬底中的有源区的隔离层。有源区是要形成闪存单元的区域。该器件还包括形成栅极叠层以跨过有源区和隔离层，并且在栅堆叠的侧壁处形成侧壁间隔物。该装置还包括一个公共源极线，其将多个闪存单元的多个源电气互连，并且通过去除隔离层中的绝缘材料而形成在隔离层中，并且与形成的字线平行地形成通过门栈。在公共源极线上形成硅化物层。

90. 发明授权

US07354841B2 Method for fabricating photodiode of CMOS image sensor 失效
标题翻译：制造CMOS图像传感器的光电二极管的方法
公开(公告)号：US07354841B2
公开(公告)日：2008-04-08
申请号：US11176721
申请日：2005-07-06
申请人： In Gyun Jeon
发明人： In Gyun Jeon
IPC分类号： H01L21/331
CPC分类号： H01L27/14601 , H01L27/14689
摘要： A method for fabricating a photodiode of a CMOS image sensor is disclosed, to improve a charge accumulation capacity in the photodiode, which includes the steps of defining a semiconductor substrate as an active area and a field area by forming an STI layer; firstly implanting impurity ions for formation of the photodiode to the semiconductor substrate of the active area; secondarily implanting impurity ions for formation of the photodiode to the semiconductor substrate being adjacent to the STI layer; and forming a photodiode ion-implantation diffusion layer by diffusing the implanted impurity ions with a thermal process.
摘要翻译：公开了一种用于制造CMOS图像传感器的光电二极管的方法，以改善光电二极管中的电荷累积能力，其包括通过形成STI层来限定半导体衬底作为有源区和场区的步骤; 首先将用于形成光电二极管的杂质离子注入有源区的半导体衬底; 二次将用于形成光电二极管的杂质离子注入到与STI层相邻的半导体衬底上; 以及通过用热处理扩散注入的杂质离子形成光电二极管离子注入扩散层。

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