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81. 发明授权

US08041110B2 Pixel interpolation method 有权
标题翻译：像素插值法
公开(公告)号：US08041110B2
公开(公告)日：2011-10-18
申请号：US12269354
申请日：2008-11-12
申请人： Hiromu Hasegawa
发明人： Hiromu Hasegawa
IPC分类号： G06K9/00
CPC分类号： H04N9/045 , G06T3/4007 , G06T3/4015 , H04N2209/046
摘要： An image processing circuit inputs pixels of an RGB Bayer array therein. A chroma value calculation circuit calculates a chroma factor (KL) for evaluating the chroma of a surrounding area of a specified pixel. A correlation value calculation circuit calculates correlation values for gray image and color image. If the chroma factor (KL) is larger than a threshold value (TH1), a correlation judgment method for color image and a pixel interpolation method for color image are selected, if the chroma factor (KL) is not larger than a threshold value (TH1) and larger than a threshold value (TH2), a correlation judgment method using a correlation value obtained by overall judgment on the correlation values for gray image and color image and a pixel interpolation method for color image are selected, and if the chroma factor (KL) is not larger than a threshold value (TH2), a correlation judgment method for gray image and a pixel interpolation method for gray image are selected.
摘要翻译：图像处理电路在其中输入RGB拜耳阵列的像素。色度值计算电路计算用于评估指定像素的周围区域的色度的色度因子（KL）。相关值计算电路计算灰度图像和彩色图像的相关值。如果色度因子（KL）大于阈值（TH1），则选择用于彩色图像的相关判断方法和彩色图像的像素插值方法，如果色度因子（KL）不大于阈值（ TH1）并且大于阈值（TH2）时，选择使用通过对灰度图像和彩色图像的相关值的总体判断获得的相关值的相关判断方法和用于彩色图像的像素插值方法，并且如果色度因子（KL）不大于阈值（TH2）时，选择灰度图像的相关判断方法和灰度图像的像素插值方法。

82. 发明授权

US07995121B2 Imaging unit, portable terminal device, and portable terminal system 有权
标题翻译：成像单元，便携式终端设备和便携式终端系统
公开(公告)号：US07995121B2
公开(公告)日：2011-08-09
申请号：US12033506
申请日：2008-02-19
申请人： Atsushi Kobayashi , Takashi Mori
发明人： Atsushi Kobayashi , Takashi Mori
IPC分类号： H04N5/262
CPC分类号： H04N9/75 , H04N5/2621 , H04N5/275
摘要： The present invention provides an imaging unit, a portable terminal device, and a portable terminal system capable of performing a satisfactory key synthesizing process. An imaging unit mainly includes an imaging section, a conversion section, and a key signal generating section. The conversion section converts the format of the imaged image data output from the imaging section from YUV format to RGB format. The key signal generating section generates a key signal based on each pixel data configuring the imaged image data and the reference data for the imaged image data input from the imaging section. The key signal generating section also outputs foreground image data having the generated key signal and the corresponding pixel data of RGB format as minimum configuring unit. An image synthesizing section of a main unit generates synthesized image data by overlapping the foreground image data from the imaging unit and the background image data stored in a RAM based on the key signal contained in the foreground image data.
摘要翻译：本发明提供了能够执行令人满意的密钥合成处理的成像单元，便携式终端装置和便携式终端系统。成像单元主要包括成像部分，转换部分和键信号产生部分。转换部分将从成像部分输出的成像图像数据的格式从YUV格式转换为RGB格式。键信号产生部分基于构成成像图像数据的每个像素数据和从成像部分输入的成像图像数据的参考数据生成键信号。键信号产生部分还输出具有生成的键信号的前景图像数据和RGB格式的相应像素数据作为最小配置单元。主单元的图像合成部分基于前景图像数据中包含的键信号，通过将来自成像单元的前景图像数据和存储在RAM中的背景图像数据重叠来产生合成图像数据。

83. 发明授权

US07979622B2 Memory access method 有权
标题翻译：内存访问方式
公开(公告)号：US07979622B2
公开(公告)日：2011-07-12
申请号：US11916127
申请日：2006-05-23
申请人： Akira Okamoto
发明人： Akira Okamoto
IPC分类号： G06F12/06
CPC分类号： G06T1/60 , G06F12/0607 , H04N19/40 , H04N19/423 , H04N19/43 , H04N19/433
摘要： A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive occurrences of access to allow for improved performance. Pieces of data are written into 0th, the first, the second, and the third banks, respectively. No idle time is caused between successive occurrences of access because different banks are successively accessed. Since a burst length of each of the pieces of data is eight, an interval of 16 cycles which is longer than 15 cycles is provided between a start of writing of first data and a start of second writing of data. Accordingly, no idle time is caused also between completion of writing of the first data and start of writing of the second data.
摘要翻译：存储器访问方法，用于在连续访问同一个存储体时在连续的访问次数之间提供预定数量的时钟周期或更长时间间隔所需的存储器，并且消除连续的访问之间的空闲时间以允许改进性能。数据分别写入第0，第1，第2，第3组。由于连续访问不同的存储区，因此在连续访问之间不会引起空闲时间。由于每个数据段的突发长度为8，所以在第一数据的写入开始和数据的第二次写入开始之间提供长于15个周期的16个周期的间隔。因此，在第一数据的写入完成和第二数据的写入开始之间也不会产生空闲时间。

84. 发明授权

US07949852B2 Memory system, computer system and memory 有权
标题翻译：内存系统，计算机系统和内存
公开(公告)号：US07949852B2
公开(公告)日：2011-05-24
申请号：US12033311
申请日：2008-02-19
申请人： Shinji Tanaka
发明人： Shinji Tanaka
IPC分类号： G06F11/22 , G06F12/00
CPC分类号： G11C29/76 , G11C16/04 , G11C29/88
摘要： The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with the physical addresses of defective blocks in a memory skipped. Then, the physical addresses of the defective blocks in ascending order are sequentially stored into the second blocks in ascending order of the physical addresses of the second blocks, respectively. To obtain a physical address from a logical address, a target block is retrieved out of a plurality of second blocks on the basis of the logical address, and the physical address of the target block is added to the logical address to obtain the physical address. Thus, it is possible to reduce the required capacity of a reserve storage region used for conversion of logical addresses into physical addresses without deteriorating the access speed.
摘要翻译：确定逻辑地址和物理地址之间的对应关系，使得按照升序排列的逻辑地址可以以跳过的内存中的缺陷块的物理地址按升序分配给物理地址。然后，分别以第二块的物理地址的升序顺序地将有序块的物理地址按升序顺序地存储到第二块中。为了从逻辑地址获取物理地址，基于逻辑地址从多个第二块中检索目标块，并且将目标块的物理地址添加到逻辑地址以获得物理地址。因此，可以将用于将逻辑地址转换为物理地址的预留存储区域的所需容量减小，而不会降低访问速度。

85. 发明授权

US07941589B2 Semiconductor memory and information processing system 有权
标题翻译：半导体存储器和信息处理系统
公开(公告)号：US07941589B2
公开(公告)日：2011-05-10
申请号：US11926533
申请日：2007-10-29
申请人： Takashi Oshikiri
发明人： Takashi Oshikiri
IPC分类号： G06F13/00
CPC分类号： G06F12/1416 , G06F2212/2022
摘要： A semiconductor memory (2) comprises a controller (21) and a memory array (22). The memory array (22) is controlled for each of block areas (221, 221 . . . ). The information processing apparatus (1) can not generate a data erase command for each block area (221). A data erase command (30) for a specified block area “G” is encoded and stored in a block area “A”. When a request for data erasing is issued, a CPU (11) of the information processing apparatus (1) reads an erase command (30) out from the semiconductor memory (2) and outputs the erase command (30) to the controller (21). The controller (21) decodes the erase command (30) and performs a data erasing process for the block area “G”.
摘要翻译：半导体存储器（2）包括控制器（21）和存储器阵列（22）。为每个块区域（221,221 ...）控制存储器阵列（22）。信息处理装置（1）不能为每个块区域生成数据擦除命令（221）。用于指定块区域“G”的数据擦除命令（30）被编码并存储在块区域“A”中。当发出数据擦除请求时，信息处理装置（1）的CPU（11）从半导体存储器（2）读出擦除指令（30），并将该擦除命令（30）输出到控制器（21））。控制器（21）对擦除命令（30）进行解码，并对块区域“G”执行数据擦除处理。

86. 发明授权

US07936931B2 Image encoding apparatus and image decoding apparatus 有权
标题翻译：图像编码装置和图像解码装置
公开(公告)号：US07936931B2
公开(公告)日：2011-05-03
申请号：US11697877
申请日：2007-04-09
申请人： Yusuke Mizuno
发明人： Yusuke Mizuno
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/423 , H04N13/359 , H04N19/129 , H04N19/63 , H04N19/645 , H04N19/647
摘要： A conversion control unit divides a transform coefficient into code blocks. A storing device has a storage capacity corresponding to data size of the code blocks. To the conversion control unit, rotation/inversion control information including information of the rotation angle and the inverting direction is input. The conversion control unit generates a control signal on the basis of the rotation/inversion control information and sub-band information of the transform coefficient. An address generating unit generates a write address on the basis of a control signal. By accessing the storing device in predetermined order on the basis of the write address at the time of writing the code block to the storing device, an image rotating/inverting process is performed.
摘要翻译：转换控制单元将变换系数划分为代码块。存储装置具有对应于代码块的数据大小的存储容量。输入到转换控制单元，输入包括旋转角度和反转方向信息的旋转/反转控制信息。转换控制单元根据变换系数的旋转/反转控制信息和子带信息生成控制信号。地址生成单元基于控制信号生成写入地址。通过基于将代码块写入存储装置时的写入地址以预定顺序访问存储装置，执行图像旋转/反转处理。

87. 发明申请

US20110075737A1 TRANSCODER 有权
公开(公告)号：US20110075737A1
公开(公告)日：2011-03-31
申请号：US12995357
申请日：2009-03-12
申请人： Makoto Saito , Hiromu Hasegawa
发明人： Makoto Saito , Hiromu Hasegawa
IPC分类号： H04N7/26 , G06K9/46
CPC分类号： H04N19/152 , H04N19/172 , H04N19/40 , H04N19/61
摘要： A generated code amount accumulation part adds up the amounts of generated codes of pictures in 1 GOP which are encoded up to the current stage. An upper limit code amount accumulation part adds up the upper limit amounts of codes of the pictures in the 1 GOP which are encoded up to the current stage. A transmission load of an image transmission system is taken into consideration in the setting of the upper limit amount of codes. An update ratio setting part outputs an update instruction to lower a target rate when the accumulated amount of generated codes exceeds the accumulated upper limit amount of codes. The update ratio setting part does not output the update instruction for lowering the target rate when the accumulated amount of generated codes does not exceed the accumulated upper limit amount of codes. A transcoder can predict whether or not there is a possibility that the load of transmitting image data will increase while each picture in 1 GOP is encoded.
摘要翻译：生成的代码量累积部分将编码到当前阶段的1个GOP中的图像的生成代码量相加。上限码量累积部分将编码到当前阶段的1 GOP中的图像的上限量的数量相加。在上限编码量的设定中考虑图像传输系统的传输负载。当累积的代码量超过累积的上限代码量时，更新比率设置部分输出更新指令以降低目标速率。当生成的代码的累积量不超过累积的上限代码量时，更新比率设置部分不输出用于降低目标速率的更新指令。代码转换器可以预测在1 GOP中的每个图像被编码时是否存在发送图像数据的负载将增加的可能性。

88. 发明授权

US07916960B2 Compression encoder, compression encoding method and program 有权
公开(公告)号：US07916960B2
公开(公告)日：2011-03-29
申请号：US11515766
申请日：2006-09-06
申请人： Yusuke Mizuno
发明人： Yusuke Mizuno
IPC分类号： G06K9/46
CPC分类号： H04N19/645 , H04N19/115 , H04N19/124 , H04N19/126 , H04N19/129 , H04N19/13 , H04N19/132 , H04N19/154 , H04N19/17 , H04N19/18 , H04N19/184 , H04N19/46 , H04N19/647 , H04N19/91
摘要： A rate control unit performs data truncation on a code sequence having been sorted and bit shifted as shown in FIG. 10 so that a desired noise reduction effect is achieved. The data truncation occurs in sequence from the rightmost bit. For example, in FIG. 10, data is truncated from data of bit 0 in a subband VHL4 downwardly in sequence through data of bit 0 in a subband YHH5, and so on. If the desired noise reduction effect can be achieved by truncation of up to bit data in the subband YHH1, data in those subbands in a dotted area in FIG. 10 will be truncated. If the desired noise reduction effect cannot be achieved by truncation of up to bit data in the subband YHH1, data will then be truncated from data of bit 0 in a subband VLL4 downwardly in sequence.

89. 发明授权

US07849277B2 Bank controller, information processing device, imaging device, and controlling method 有权
标题翻译：银行控制器，信息处理设备，成像设备和控制方法
公开(公告)号：US07849277B2
公开(公告)日：2010-12-07
申请号：US11625636
申请日：2007-01-22
申请人： Takashi Matsutani
发明人： Takashi Matsutani
IPC分类号： G06F13/18
CPC分类号： G06F13/28
摘要： A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priorities in data communication performed between FIFO memories and associated banks. A precharge period detecting block detects the states of precharge of the banks. A register stores data required to determine the order of priorities (data indicating whether the banks are in a precharge period, data indicating whether data communication request signals are presented). This enables the arbiter to exclude FIFO memories that are associated with banks that are not allowed to perform data communication. Efficient data communication is thus implemented between the FIFO memories and the synchronous DRAM.
摘要翻译：提供了一种银行控制器，信息处理装置，成像装置和控制方法，其能够改进处理块的FIFO存储器和同步DRAM之间的数据通信处理。仲裁器确定在FIFO存储器和关联存储体之间执行的数据通信中的优先顺序。预充电周期检测块检测银行的预充电状态。寄存器存储确定优先级顺序所需的数据（指示存储体是否在预充电期间的数据，表示是否呈现数据通信请求信号的数据）。这使得仲裁器能够排除与不允许执行数据通信的存储体相关联的FIFO存储器。因此，在FIFO存储器和同步DRAM之间实现有效的数据通信。

90. 发明申请

US20100268729A1 MULTIMEDIA SYNTHETIC DATA GENERATING APPARATUS 审中-公开
标题翻译：多媒体综合数据生成设备
公开(公告)号：US20100268729A1
公开(公告)日：2010-10-21
申请号：US12741377
申请日：2008-11-10
申请人： Yusuke Nara , Junya Tsutsumi , Junichi Nishiyama , Manabu Kawamoto
发明人： Yusuke Nara , Junya Tsutsumi , Junichi Nishiyama , Manabu Kawamoto
IPC分类号： G06F17/30 , G06K9/00
CPC分类号： H04N5/91 , G11B27/105 , H04N1/00198 , H04N1/00307 , H04N1/32128 , H04N5/23293 , H04N5/2621 , H04N5/765 , H04N5/772 , H04N5/783 , H04N5/907 , H04N9/8205 , H04N2101/00 , H04N2201/3214 , H04N2201/3253 , H04N2201/3274
摘要： A technique for drawing or managing multimedia data by desired groups. In a built-in memory of a cellular phone terminal, thirteen picked-up image data are stored. In tag information of each of the thirteen picked-up image data, information on date and time is recorded when an image of the data is picked up. When a user specifies the range of image pickup date and time, eight picked-up image data that match the specified range of image pickup date and time are selected and synthetic image data is generated from these eight picked-up image data.
摘要翻译：用于绘制或管理所需组的多媒体数据的技术。在蜂窝电话终端的内置存储器中，存储13个拾取图像数据。在十三个拍摄图像数据中的每一个的标签信息中，当拾取数据的图像时记录关于日期和时间的信息。当用户指定图像摄取日期和时间的范围时，选择与指定的摄像日期和时间范围相匹配的8个拾取图像数据，并且从这8个拾取图像数据生成合成图像数据。

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