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81. 发明申请

US20200174945A1 Managing Translation Lookaside Buffer Entries Based on Associativity and Page Size 审中-公开
公开(公告)号：US20200174945A1
公开(公告)日：2020-06-04
申请号：US16204722
申请日：2018-11-29
申请人： Marvell International Ltd.
发明人： Shubhendu Sekhar Mukherjee , Richard Eugene Kessler , Michael Bertone
IPC分类号： G06F12/1036
摘要： A first cache module, comprising fully associative cache circuitry, provides TLB entries for a first group of multiple page sizes. A second cache module, comprising set associative cache circuitry, provides TLB entries for a second group of multiple page sizes. Managing TLB entries includes: performing a search in the first cache module based on selected tag bits of a target virtual address that are selected for each TLB entry in the first cache module based on information stored in the first cache module corresponding to one of the multiple pages sizes in the first group, and performing multiple search iterations in the second cache module based on selected index bits and selected tag bits of the target virtual address, where quantities of bits in the selected index bits and the selected tag bits are different for each of the search iterations.

82. 发明授权

US10664400B2 Address translation cache partitioning 有权
公开(公告)号：US10664400B2
公开(公告)日：2020-05-26
申请号：US15646406
申请日：2017-07-11
申请人： ARM Limited
发明人： Andrew Brookfield Swaine
IPC分类号： G06F12/0846 , G06F12/0808 , G06F12/1009 , G06F12/1036
摘要： An apparatus has an address translation cache with entries for storing address translation data. Partition configuration storage circuitry stores multiple sets of programmable configuration data each corresponding to a partition identifier identifying a corresponding software execution environment or master device and specifying a corresponding subset of entries of the cache. In response to a translation lookup request specifying a target address and a requesting partition identifier, control circuitry triggers a lookup operation to identify whether the target address hits or misses in the corresponding subset of entries specified by the set of partition configuration data for the requesting partition identifier.

83. 发明授权

US10649814B2 Device, method, and medium for executing a computing process within an accessed monitoring region 有权
公开(公告)号：US10649814B2
公开(公告)日：2020-05-12
申请号：US16035118
申请日：2018-07-13
申请人： FUJITSU LIMITED
发明人： Amir Haderbache , Saso Stanovnik , Masahiro Miwa , Kohta Nakashima
IPC分类号： G06F9/455 , G06F9/50 , G06F12/1036 , G06F12/02 , G06F12/14 , G06N3/08
摘要： An information processing device includes a memory storing information indicating a virtual address space for data to be processed; and a processor that executes, via the virtual address space, a given process on the data to be processed, monitors access from the processor to multiple monitoring regions among a plurality of regions included in the virtual address space and have been set as targets to be monitored, and executes given control based on an accessed monitoring region among the multiple monitoring regions and for which the access has been detected by the processor.

84. 发明授权

US10599582B2 Using a virtual to virtual address table for memory compression 有权
公开(公告)号：US10599582B2
公开(公告)日：2020-03-24
申请号：US15276025
申请日：2016-09-26
申请人： Intel Corporation
发明人： Vidhya Krishnan , Niranjan L. Cooray , Murali Ramadoss
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/1009 , G06F12/0802 , G06F12/1045 , G06F12/1036 , G06F12/10
摘要： A virtual-to-virtual page table maps a main surface containing the actual data and a metadata or auxiliary surface that gives information about compression of the main surface. In order to access the metadata that corresponds to main surface, an additional virtual-to-virtual table may be used ahead of the regular page table mapping to avoid the need to pass the metadata base address and x, y coordinates across a pipeline which may result in multiple memory writes.

85. 发明授权

US10545879B2 Apparatus and method for handling access requests 有权
公开(公告)号：US10545879B2
公开(公告)日：2020-01-28
申请号：US15935203
申请日：2018-03-26
申请人： Arm Limited
发明人： Richard F. Bryant , Kim Richard Schuttenberg , David Madsen , Lalit Bansal , Sriram Samynathan
IPC分类号： G06F12/08 , G06F12/1036 , G06F12/109 , G06F12/1045 , G06F12/0815 , G06F12/0846
摘要： An apparatus and method are provided for handling access requests. The apparatus has processing circuitry for processing a plurality of program threads to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. The cache storage has a plurality of cache entries to store data, an aliasing condition existing when multiple virtual addresses map to the same physical address, and allocation of data into the cache storage being constrained to prevent multiple cache entries of the cache storage simultaneously storing data for the same physical address. Cache access circuitry is then responsive to an access request specifying a virtual address, to utilise a cache index at least partially determined from the specified virtual address to identify at least one cache entry within the cache storage, and to detect whether a hit is present within the at least one cache entry by comparing a physical address portion associated with that cache entry with a tag portion of the physical address corresponding to the specified virtual address. Remap handling circuitry is then arranged whilst a first program thread is in the process of performing an exclusive operation using a first virtual address to identify a specified physical address whose data is stored in the cache storage, to detect a remap condition when a second program thread issues a second program thread access request of at least one type that specifies a second virtual address that exhibits the aliasing condition with the first virtual address. In the presence of the remap condition, the remap handling circuitry remaps the cache index at least partially determined from the second virtual address, so that the remapped cache index as then used by the cache access circuitry matches the cache index at least partially determined from the first virtual address. This provides an effective mechanism for avoiding potential live-lock scenarios that can otherwise arise.

86. 发明授权

US10409715B2 Memory controller, nonvolatile memory system, and operating method thereof 有权
公开(公告)号：US10409715B2
公开(公告)日：2019-09-10
申请号：US15483255
申请日：2017-04-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sung-Hwan Bae , Chan-Ik Park , Hyun-Jin Choi , Seong-Jun Ahn , In-Hwan Doh
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/02 , G06F12/0873 , G06F12/1036 , G06F12/14 , G06F21/78
摘要： In an operating method of a memory controller, the memory controller includes a logical-to-logical (L2L) mapping table including mapping information between a first logical area and a second logical area and a logical-to-physical (L2P) mapping table including mapping information between the second logical area and a physical area of a memory device. The operating method includes receiving a first logical address of the first logical area and a first command for changing the L2L mapping table to access first data stored in the memory device through the first logical address, detecting a second logical address of the second logical area mapped to a physical address of the physical area in which the first data is stored, in response to the first command, and changing the L2L mapping table to map the first logical address to the second logical address.

87. 发明申请

US20190236024A1 MULTI-ENGINE ADDRESS TRANSLATION FACILITY 审中-公开
公开(公告)号：US20190236024A1
公开(公告)日：2019-08-01
申请号：US16377509
申请日：2019-04-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Uwe BRANDT , Markus HELMS , Christian JACOBI , Markus KALTENBACH , Thomas KOEHLER , Frank LEHNERT
IPC分类号： G06F12/1036 , G06F12/1009
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/1009 , G06F2009/45583 , G06F2212/1016 , G06F2212/1056 , G06F2212/151 , G06F2212/651 , G06F2212/657 , G06F2212/681 , G06F2212/684
摘要： An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

88. 发明授权

US10365858B2 Thin provisioning in a storage device 有权
公开(公告)号：US10365858B2
公开(公告)日：2019-07-30
申请号：US14073637
申请日：2013-11-06
申请人： PURE STORAGE, INC.
发明人： Ethan Miller , John Colgrove , John Hayes
IPC分类号： G06F3/06 , G06F12/1009 , G06F12/1036
摘要： An apparatus, method, and computer-readable storage medium for allowing a block-addressable storage device to provide a sparse address space to a host computer. The storage device exports an address space to a host computing device which is larger than the storage capacity of the storage device. The storage device translates received file system object addresses in the larger address space to physical locations in the smaller address space of the storage device. This allows the host computing device more flexibility in selecting addresses for file system objects which are stored on the storage device.

89. 发明申请

US20190205261A1 SYSTEMS, METHODS, AND APPARATUSES FOR PATCHING PAGES 审中-公开
公开(公告)号：US20190205261A1
公开(公告)日：2019-07-04
申请号：US15858262
申请日：2017-12-29
申请人： Intel Corporation
发明人： David CHERITON
IPC分类号： G06F12/1036 , G06F9/455
CPC分类号： G06F12/1036 , G06F9/45558 , G06F2009/45583 , G06F2212/151 , G06F2212/50 , G06F2212/657
摘要： Systems, methods, and apparatuses for patching pages are described. For example, a method comprising: allocating a small size page and initializing the small size page; adding the allocated and initialized small size page to a small size page table to reflect usage of a patch of the huge size page; and setting an indication of usage of the patch in a page entry associated with the huge size page is described.

90. 发明授权

US10282306B2 Supporting secure memory intent 有权
公开(公告)号：US10282306B2
公开(公告)日：2019-05-07
申请号：US15861364
申请日：2018-01-03
申请人： INTEL CORPORATION
发明人： Krystof C. Zmudzinski , Siddhartha Chhabra , Uday R. Savagaonkar , Simon P. Johnson , Rebekah M. Leslie-Hurd , Francis X. McKeen , Gilbert Neiger , Raghunandan Makaram , Carlos V. Rozas , Amy L. Santoni , Vincent R. Scarlata , Vedvyas Shanbhogue , Ilya Alexandrovich , Ittai Anati , Wesley H. Smith , Michael Goldsmith
IPC分类号： G06F12/14 , G06F9/455 , G06F12/109 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/1045
摘要： A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

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