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81. 发明申请

US20070013008A1 Power LDMOS transistor 有权
公开(公告)号：US20070013008A1
公开(公告)日：2007-01-18
申请号：US11180155
申请日：2005-07-13
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L21/337
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7811 , H01L29/7823
摘要： An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.

82. 发明授权

US07101741B2 Dual double gate transistor and method for forming 有权
公开(公告)号：US07101741B2
公开(公告)日：2006-09-05
申请号：US10780393
申请日：2004-02-17
申请人： David M. Fried , Edward J. Nowak
发明人： David M. Fried , Edward J. Nowak
IPC分类号： H01L21/337
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： The present invention provides a dual gate transistor and a method for forming the same that results in improved device performance and density. The present invention uses a double gate design to implement a dual gate transistor. A double gate is a gate which is formed on both sides of the transistor body. The present invention thus provides a transistor with two double gates in series that provide improved current control over traditional dual gate designs. The preferred embodiment of the present invention uses a fin type body with dual double-gates. In a fin type structure, the double gates are formed on each side of a thin fin shaped body, with the body being disposed horizontally between the gates.

83. 发明授权

US07087472B2 Method of making a vertical compound semiconductor field effect transistor device 有权
标题翻译：制造垂直化合物半导体场效应晶体管器件的方法
公开(公告)号：US07087472B2
公开(公告)日：2006-08-08
申请号：US10623392
申请日：2003-07-18
申请人： Peyman Hadizad
发明人： Peyman Hadizad
IPC分类号： H01L21/337
CPC分类号： H01L29/66856 , H01L29/8122
摘要： In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate region is then formed on the sidewalls and the bottom surface of the second trench. Source regions are formed on opposite sides of the trench structure. Localized gate contact regions couple individual doped gate regions together. Contacts are then formed to the localized gate contact regions, the source regions, and an opposing surface of the body of semiconductor material. The method provides a compound semiconductor vertical FET structure having enhanced blocking capability.
摘要翻译：在一个实施例中，一种用于制造化合物半导体垂直FET器件的方法包括在半导体材料体中形成第一沟槽，以及在第一沟槽内形成自对准的第二沟槽以限定沟道区。然后在第二沟槽的侧壁和底表面上形成掺杂栅极区域。源极区域形成在沟槽结构的相对侧上。局部栅极接触区将各个掺杂的栅极区域耦合在一起。接触件然后形成到局部栅极接触区域，源极区域和半导体材料体的相对表面。该方法提供了具有增强的阻挡能力的化合物半导体垂直FET结构。

84. 发明授权

US07067363B2 Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density 有权
标题翻译：具有双重栅极氧化物的垂直导通和平面结构的MOS器件和用于实现具有改善的静态和动态性能以及高缩小密度的功率垂直MOS晶体管的方法
公开(公告)号：US07067363B2
公开(公告)日：2006-06-27
申请号：US10749134
申请日：2003-12-30
申请人： Angelo Magri′ , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
发明人： Angelo Magri′ , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
IPC分类号： H01L21/337 , H01L29/80 , H01L31/112
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

85. 发明授权

US07064038B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US07064038B2
公开(公告)日：2006-06-20
申请号：US10754577
申请日：2004-01-12
申请人： Hiroshi Kudo , Junko Naganuma , Sadahiro Kishii
发明人： Hiroshi Kudo , Junko Naganuma , Sadahiro Kishii
IPC分类号： H01L21/336 , H01L21/338 , H01L21/337 , H01L21/44
CPC分类号： H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/66606
摘要： The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.

86. 发明申请

US20060071247A1 Reliable high-voltage junction field effect transistor and method of manufacture therefor 有权
标题翻译：可靠的高压结场效应晶体管及其制造方法
公开(公告)号：US20060071247A1
公开(公告)日：2006-04-06
申请号：US10956863
申请日：2004-10-01
申请人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
发明人： Kaiyuan Chen , Joe Trogolo , Tathagata Chatterjee , Steve Merchant
IPC分类号： H01L21/337 , H01L29/80
CPC分类号： H01L29/402 , H01L29/1066 , H01L29/41725 , H01L29/42316 , H01L29/66901 , H01L29/808
摘要： The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410). In place of or addition to the doped region (810), the high-voltage junction field effect transistor (JFET) (300) may includes a conductive field plate (920) located over and extending along the width of the gate region (410).
摘要翻译：本发明提供一种高电压结型场效应晶体管（JFET），一种制造方法和包括该高压结型场效应晶体管的集成电路。高压结场效应晶体管（JFET）（300）的一个实施例包括位于衬底（318）内的第一导电类型的阱区（320）和位于衬底（318）内的第二导电类型的栅极区（410）所述阱区域（320），所述栅极区域（410）具有长度和宽度。该实施例还包括与栅极区域（410）间隔开的位于衬底（318）内的第一导电类型的源极区（710）和漏极区（715），以及掺杂区位于栅极区域（410）中并沿着栅极区域（410）的宽度延伸的第二导电类型。高电压结场效应晶体管（JFET）300可代替或添加到掺杂区域（810），包括位于栅极区域（410）的宽度上方且沿栅极区域（410）的宽度延伸的导电场板（920）。

87. 发明授权

US07022560B2 Method to manufacture high voltage MOS transistor by ion implantation 有权
标题翻译：通过离子注入制造高压MOS晶体管的方法
公开(公告)号：US07022560B2
公开(公告)日：2006-04-04
申请号：US10853508
申请日：2004-05-25
申请人： Peter Olofsson
发明人： Peter Olofsson
IPC分类号： H01L21/337 , H01L21/336
CPC分类号： H01L29/1087 , H01L21/26586 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L29/1083 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A method for fabrication of a high-voltage, high-frequency MOS-transistor combines a deep n-well and a p-well process and the formation of an extended drain region (45), and a channel region (31), the channel having a short length and becoming well aligned with the gate edge. The deep n-well (11) and the p-well (19) are both produced by ion implantation. The method is compatible with a standard CMOS process and gives low manufacturing costs, increased breakdown voltage, better overall high-frequency performance, and the prevention of the “body effect” occurring by isolation of the p-well.
摘要翻译：一种用于制造高电压，高频MOS晶体管的方法组合了深n阱和p阱工艺，并形成扩展漏极区（45）和沟道区（31），沟道具有短的长度并且与栅极边缘良好地对齐。深n阱（11）和p阱（19）均通过离子注入产生。该方法与标准CMOS工艺兼容，并且制造成本低，击穿电压提高，整体高频性能更好，并且通过隔离p阱来防止“身体效应”。

88. 发明申请

US20050250302A1 Thin films and methods of making them 有权
标题翻译：薄膜及其制作方法
公开(公告)号：US20050250302A1
公开(公告)日：2005-11-10
申请号：US11179256
申请日：2005-07-12
申请人： Michael Todd , Ivo Raaijmakers
发明人： Michael Todd , Ivo Raaijmakers
IPC分类号： C23C16/24 , C23C16/02 , C23C16/42 , C30B25/02 , H01L21/20 , H01L21/205 , H01L21/28 , H01L21/285 , H01L21/316 , H01L21/331 , H01L21/337 , H01L21/425 , H01L21/469 , H01L21/8238 , H01L27/092 , H01L29/51 , H01L29/737 , H01L29/78 , H01L31/18 , H01L31/20 , H01L21/66 , G01R31/26 , H01L21/00 , H01L21/44 , H01L21/84
CPC分类号： C23C16/0272 , B82Y10/00 , B82Y30/00 , C23C16/22 , C23C16/24 , C23C16/30 , C23C16/308 , C23C16/325 , C23C16/345 , C23C16/36 , C23C16/56 , C30B25/02 , C30B29/06 , H01L21/02422 , H01L21/0243 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02592 , H01L21/02595 , H01L21/02598 , H01L21/0262 , H01L21/02667 , H01L21/2257 , H01L21/28035 , H01L21/28044 , H01L21/28194 , H01L21/28525 , H01L21/28556 , H01L21/3185 , H01L21/32055 , H01L28/84 , H01L29/127 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66181 , H01L29/66242 , H01L31/1804 , H01L31/182 , H01L31/202 , Y02E10/546 , Y02E10/547 , Y02P70/521 , Y10S438/933
摘要： Thin, smooth silicon-containing films are prepared by deposition methods that utilize a silicon containing precursor. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 Å or less, a surface roughness of about 5 Å rms or less, and a thickness non-uniformity of about 20% or less. Preferred silicon-containing films display a high degree of compositional uniformity when doped or alloyed with other elements. Preferred deposition methods provide improved manufacturing efficiency and can be used to make various useful structures such as wetting layers, HSG silicon, quantum dots, dielectric layers, anti-reflective coatings (ARC's), gate electrodes and diffusion sources.
摘要翻译：通过使用含硅前体的沉积方法制备薄的，平滑的含硅膜。在优选的实施方案中，该方法产生连续的并且具有约150或更小的厚度，约5μm或更小的表面粗糙度和约20％或更小的厚度不均匀性的含Si膜。当与其它元素掺杂或合金化时，优选的含硅膜显示出高度的组成均匀性。优选的沉积方法提供了改进的制造效率，并且可以用于制备各种有用的结构，例如润湿层，HSG硅，量子点，电介质层，抗反射涂层（ARC），栅电极和扩散源。

89. 发明授权

US06962859B2 Thin films and method of making them 有权
标题翻译：薄膜及其制作方法
公开(公告)号：US06962859B2
公开(公告)日：2005-11-08
申请号：US10074564
申请日：2002-02-11
申请人： Michael A. Todd , Ivo Raaijmakers
发明人： Michael A. Todd , Ivo Raaijmakers
IPC分类号： C23C16/24 , C23C16/02 , C23C16/42 , C30B25/02 , H01L21/20 , H01L21/205 , H01L21/28 , H01L21/285 , H01L21/316 , H01L21/331 , H01L21/337 , H01L21/425 , H01L21/469 , H01L21/8238 , H01L27/092 , H01L29/51 , H01L29/737 , H01L29/78 , H01L31/18 , H01L31/20
CPC分类号： C23C16/0272 , B82Y10/00 , B82Y30/00 , C23C16/22 , C23C16/24 , C23C16/30 , C23C16/308 , C23C16/325 , C23C16/345 , C23C16/36 , C23C16/56 , C30B25/02 , C30B29/06 , H01L21/02422 , H01L21/0243 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02592 , H01L21/02595 , H01L21/02598 , H01L21/0262 , H01L21/02667 , H01L21/2257 , H01L21/28035 , H01L21/28044 , H01L21/28194 , H01L21/28525 , H01L21/28556 , H01L21/3185 , H01L21/32055 , H01L28/84 , H01L29/127 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66181 , H01L29/66242 , H01L31/1804 , H01L31/182 , H01L31/202 , Y02E10/546 , Y02E10/547 , Y02P70/521 , Y10S438/933
摘要： Thin, smooth silicon-containing films are prepared by deposition methods that utilize a silicon-containing precursor. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 Å or less, a surface roughness of about 5 Å rms or less, and a thickness non-uniformity of about 20% or less. Preferred silicon-containing films display a high degree of compositional uniformity when doped or alloyed with other elements. Preferred deposition methods provide improved manufacturing efficiency and can be used to make various useful structures such as wetting layers, HSG silicon, quantum dots, dielectric layers, anti-reflective coatings (ARC's), gate electrodes and diffusion sources.
摘要翻译：通过使用含硅前体的沉积方法制备薄且平滑的含硅膜。在优选的实施方案中，该方法产生连续的并且具有约150或更小的厚度，约5μm或更小的表面粗糙度和约20％或更小的厚度不均匀性的含Si膜。当与其它元素掺杂或合金化时，优选的含硅膜显示出高度的组成均匀性。优选的沉积方法提供了改进的制造效率，并且可以用于制备各种有用的结构，例如润湿层，HSG硅，量子点，电介质层，抗反射涂层（ARC），栅电极和扩散源。

90. 发明申请

US20050233532A1 Method of forming sidewall spacers 审中-公开
标题翻译：形成侧墙的方法
公开(公告)号：US20050233532A1
公开(公告)日：2005-10-20
申请号：US11039084
申请日：2005-01-19
申请人： Markus Lenski , Falk Graetsch , Carsten Reichel , Christoph Schwan , Helmut Bierstedt , Thorsten Kammler , Martin Mazur
发明人： Markus Lenski , Falk Graetsch , Carsten Reichel , Christoph Schwan , Helmut Bierstedt , Thorsten Kammler , Martin Mazur
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/337 , H01L29/45 , H01L29/74 , H01L29/78 , H01L31/111
CPC分类号： H01L21/31144 , H01L21/32139 , H01L29/6659 , H01L29/7833
摘要： The present invention allows the formation of sidewall spacers adjacent a feature on a substrate without there being an undesirable erosion of the feature. The feature is covered by one or more protective layers. A layer of a spacer material is deposited over the feature and etched anisotropically. An etchant used in the anisotropic etching is adapted to selectively remove the spacer material, whereas the one or more protective layers are substantially not affected by the etchant. Thus, the one or more protective layers protect the feature from being exposed to the etchant.
摘要翻译：本发明允许在衬底上形成与特征相邻的侧壁间隔件，而不会有不希望的特征侵蚀。该特征被一个或多个保护层覆盖。隔离材料层沉积在特征上并各向异性地蚀刻。在各向异性蚀刻中使用的蚀刻剂适于选择性地去除间隔物材料，而一个或多个保护层基本上不受蚀刻剂的影响。因此，一个或多个保护层保护特征不暴露于蚀刻剂。

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