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81. 发明申请

US20230005796A1 TRENCH ISOLATION WITH CONDUCTIVE STRUCTURES 有权
公开(公告)号：US20230005796A1
公开(公告)日：2023-01-05
申请号：US17815094
申请日：2022-07-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chandrashekhar Prakash SAVANT , Chia-Ming TSAI , Yuh-Ta FAN , Tien-Wei YU
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/3213 , H01L27/092 , H01L29/49
摘要： The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.

82. 发明授权

US11545491B2 Fin field-effect transistor and method of forming the same 有权
公开(公告)号：US11545491B2
公开(公告)日：2023-01-03
申请号：US17199539
申请日：2021-03-12
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Te-Hsin Chiu , Kam-Tou Sio , Jiann-Tyng Tzeng
IPC分类号： H01L27/092 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/786 , H01L29/78 , H01L21/764 , H01L21/8238 , H01L23/528
摘要： A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.

83. 发明申请

US20220416044A1 LATERAL CONFINEMENT OF SOURCE DRAIN EPITAXIAL GROWTH IN NON-PLANAR TRANSISTOR FOR CELL HEIGHT SCALING 有权
公开(公告)号：US20220416044A1
公开(公告)日：2022-12-29
申请号：US17359440
申请日：2021-06-25
申请人： Intel Corporation
发明人： Nitesh KUMAR , Mohammed HASAN , Vivek THIRTHA , Nikhil MEHTA , Tahir GHANI
IPC分类号： H01L29/423 , H01L29/06 , H01L29/786 , H01L29/08 , H01L27/092
摘要： Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires. The epitaxial growth occurs inside a mold confinement, and due the mold, the lateral wingspan of the wingspan of the epitaxial growth is limited. Also the mold causes the epitaxial source or drain structures to exhibit substantially vertical opposing sidewalls and a top surface having a generally mushroom shape over a top of a dielectric layer.

84. 发明申请

US20220416024A1 GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING UNDERLYING DOPANT-DIFFUSION BLOCKING LAYERS 有权
公开(公告)号：US20220416024A1
公开(公告)日：2022-12-29
申请号：US17903914
申请日：2022-09-06
申请人： Intel Corporation
发明人： Glenn GLASS , Anand MURTHY , Biswajeet GUHA , Dax CRUM , Patrick KEYS , Tahir GHANI , Susmita GHOSE , Ted COOK, JR.
IPC分类号： H01L29/06 , H01L21/265 , H01L29/78 , H01L21/306 , H01L29/66 , H01L21/308 , H01L21/02 , H01L29/165 , H01L29/10 , H01L29/08 , H01L29/423 , H01L21/3213 , H01L21/027 , H01L27/092 , H01L21/683 , H01L21/8238
摘要： Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

85. 发明申请

US20220415905A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
公开(公告)号：US20220415905A1
公开(公告)日：2022-12-29
申请号：US17929513
申请日：2022-09-02
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-Bum KIM , Myung-Gil KANG , Kang-Hun MOON , Cho-Eun LEE , Su-Jin JUNG , Min-Hee CHOI , Yang XU , Dong-Suk SHIN , Kwan-Heum LEE , Hoi-Sung CHUNG
IPC分类号： H01L27/11 , H01L23/528 , H01L29/66 , H01L27/088 , H01L29/161 , H01L21/8234 , H01L29/08 , H01L29/78 , H01L29/45 , H01L29/417 , H01L23/485 , H01L27/092 , H01L29/165
摘要： A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

86. 发明授权

US11538915B2 Semiconductor device 有权
公开(公告)号：US11538915B2
公开(公告)日：2022-12-27
申请号：US17163589
申请日：2021-02-01
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Yu Yang
IPC分类号： H01L29/423 , H01L27/092 , H01L29/786
摘要： A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. A material composition of the first vertical portion is identical to a material composition of each of the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.

87. 发明授权

US11538813B2 Static random access memory and method for fabricating the same 有权
公开(公告)号：US11538813B2
公开(公告)日：2022-12-27
申请号：US16923117
申请日：2020-07-08
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ching-Wen Hung , Chun-Hsien Lin , Chien-Hung Chen
IPC分类号： H01L27/11 , H01L27/092 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L21/285 , H01L29/45
摘要： A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

88. 发明授权

US11538806B2 Gate-all-around integrated circuit structures having high mobility 有权
公开(公告)号：US11538806B2
公开(公告)日：2022-12-27
申请号：US16143951
申请日：2018-09-27
申请人： Intel Corporation
发明人： Roza Kotlyar , Rishabh Mehandru , Stephen Cea , Biswajeet Guha , Dax Crum , Tahir Ghani
IPC分类号： H01L29/78 , H01L29/66 , H01L27/092 , H01L21/8238 , H01L29/06 , H01L29/08 , H01L29/49
摘要： Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

89. 发明授权

US11532728B2 Method semiconductor device fabrication with improved epitaxial source/drain proximity control 有权
公开(公告)号：US11532728B2
公开(公告)日：2022-12-20
申请号：US16696261
申请日：2019-11-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Fu-Tsun Tsai , Tong Jun Huang , I-Chih Chen , Chi-Cherng Jeng
IPC分类号： H01L27/088 , H01L29/78 , H01L29/08 , H01L27/092 , H01L29/66 , H01L21/02 , H01L29/165 , H01L21/8234 , H01L21/311 , H01L21/8238
摘要： A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.

90. 发明授权

US11532519B2 Semiconductor device and method 有权
公开(公告)号：US11532519B2
公开(公告)日：2022-12-20
申请号：US17340660
申请日：2021-06-07
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yi-Bo Liao , Kai-Chieh Yang , Ching-Wei Tsai , Kuan-Lun Cheng
IPC分类号： H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/66 , H01L21/02 , H01L21/28 , H01L21/306 , H01L21/3065 , H01L27/092
摘要： In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

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