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1. 发明申请

US20230120783A1 DECOUPLED ACCESS-EXECUTE PROCESSING AND PREFETCHING CONTROL 有权
公开(公告)号：US20230120783A1
公开(公告)日：2023-04-20
申请号：US17905225
申请日：2020-12-21
申请人： ARM LIMITED
发明人： Mbou EYOLE , Michiel Willem VAN TOL , Stefanos KAXIRAS
IPC分类号： G06F9/38
摘要： Apparatuses and methods are provided, relating to the control of data processing in devices which comprise both decoupled access-execute processing circuitry and prefetch circuitry. Control of the access portion of the decoupled access-execute processing circuitry may be dependent on a performance metric of the prefetch circuitry. Alternatively or in addition, control of the prefetch circuitry may be dependent on a performance metric of the access portion.

2. 发明授权

US11625316B2 Checksum generation 有权
公开(公告)号：US11625316B2
公开(公告)日：2023-04-11
申请号：US16740737
申请日：2020-01-13
申请人： Arm Limited
发明人： Spyros Lyberis , Richard William Earnshaw
IPC分类号： G06F11/36 , G06F9/30 , G06F9/54 , G06F11/32 , H03M13/09
摘要： An apparatus has processing circuitry to perform data processing in response to instructions; at least one control storage element to store internal state for controlling operation of the processing circuitry; and checksum generating circuitry to generate a checksum based on at least one item of internal state stored in the at least one control storage element. The checksum is stored in a diagnostic storage location from which information is accessible to a diagnostic control agent (e.g. software executing on the processing circuitry and/or an external device). This makes design of software test libraries for detecting hardware faults much more efficient.

3. 发明授权

US11620217B2 Partition identifier space selection 有权
公开(公告)号：US11620217B2
公开(公告)日：2023-04-04
申请号：US17218718
申请日：2021-03-31
申请人： Arm Limited
发明人： Steven Douglas Krueger , Yuval Elad
IPC分类号： G06F12/0802 , G06F3/06
摘要： Processing circuitry processes instructions in one of at least three domains each associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request comprising a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment which caused the memory access request to be issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from among at least three partition identifier spaces based on a current domain of the processing circuitry). The selected partition identifier space and partition identifier together represent information for selecting, at a memory system component, parameters for controlling allocation of resources for handling the memory access request or managing contention for said resources, or for selecting whether performance monitoring data is updated in response to the memory access request.

4. 发明授权

US11615022B2 Apparatus and method for handling accesses targeting a memory 有权
公开(公告)号：US11615022B2
公开(公告)日：2023-03-28
申请号：US16943121
申请日：2020-07-30
申请人： Arm Limited
发明人： Lorenzo Di Gregorio , Andrew Brookfield Swaine
IPC分类号： G06F12/0811 , G06F1/3206 , G06F1/3296 , G06F12/0815
摘要： An apparatus is described that has processing circuitry for performing operations, and a communication path employed by the processing circuitry to access a first memory. Switch circuitry, when activated, is connected to the communication path. The processing circuitry issues access commands specifying addresses to be accessed, where each address is mapped to location in a memory system in accordance with a system address map. The memory system comprises at least the first memory and a second memory. When in a particular mode, the processing circuitry performs operations that require access to only a subset of the locations provided in the first memory. The switch circuitry is arranged, whilst the processing circuitry is in the particular mode, to be activated in order to intercept the access commands issued over the communication path that specify addresses mapped by the system address map to locations within the subset of locations. Those intercepted access commands are redirected to locations within the second memory that are otherwise unused whilst the processing circuitry is in the particular mode. This can provide significant power consumption benefits.

5. 发明申请

US20230088780A1 PROFILING OF SAMPLED OPERATIONS PROCESSED BY PROCESSING CIRCUITRY 有权
公开(公告)号：US20230088780A1
公开(公告)日：2023-03-23
申请号：US17999167
申请日：2021-05-20
申请人： Arm Limited
发明人： Michael John WILLIAMS , Alasdair GRANT , John Michael HORLEY
IPC分类号： G06F9/34 , G06F9/26 , G06F9/38
摘要： Processing circuitry performs data processing operations in response to instructions fetched from a cache or memory or micro-operations decoded from the instructions. Sampling circuitry selects a subset of instructions or micro-operations as sampled operations to be profiled. Profiling circuitry captures, in response to processing of an instruction or micro-operation selected as a sampled operation, a sample record specifying an operation type of the sampled operation and information about behaviour of the sampled operation which is directly attributed to the sampled operation. The profiling circuitry can include, in the sample record for a sampled operation corresponding to a given instruction, a reference instruction address indicator indicative of an address of a reference instruction appearing earlier or later in program order than the given instruction, for which control flow is sequential between any instructions occurring between the reference instruction and the given instruction in program order.

6. 发明申请

US20230079210A1 Method and Apparatus for Changing Address-to-Row Mappings in a Skewed-Associative Cache 有权
公开(公告)号：US20230079210A1
公开(公告)日：2023-03-16
申请号：US17471406
申请日：2021-09-10
申请人： Arm Limited
发明人： Alexander Klimov
IPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0877
摘要： Systems, devices and methods are provided for operating a skewed-associative cache in a data processing system and, in particular, for changing address-to-row mappings in a skewed-associative cache.

7. 发明授权

US11604727B2 Apparatus and methods to prolong lifetime of memories 有权
公开(公告)号：US11604727B2
公开(公告)日：2023-03-14
申请号：US16478544
申请日：2018-01-09
申请人： Arm Limited
发明人： Ireneus Johannes de Jong , Andres Amaya Garcia , Stephan Diestelhorst
IPC分类号： G06F12/02 , G06F12/0868 , G06F12/0873 , G06F11/07 , G11C11/409
摘要： Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

8. 发明申请

US20230076138A1 Nibble Block Format 有权
公开(公告)号：US20230076138A1
公开(公告)日：2023-03-09
申请号：US17470470
申请日：2021-09-09
申请人： Arm Limited
发明人： Paul Nicholas Whatmough , Zhi-Gang Liu , Matthew Mattina
IPC分类号： G06F17/16 , G06F7/544 , G06F7/523 , G06F7/50 , G06F9/50
摘要： A matrix multiplication system and method are provided. The system includes a memory that stores one or more weight tensors, a processor and a matrix multiply accelerator (MMA). The processor converts each weight tensor into an encoded block set that is stored in the memory. Each encoded block set includes a number of encoded blocks, and each encoded block includes a data field and an index field. The MMA converts each encoded block set into a reconstructed weight tensor, and convolves each reconstructed weight tensor and an input data tensor to generate an output data matrix.

9. 发明申请

US20230067573A1 PREDICATED VECTOR LOAD MICRO-OPERATION 有权
公开(公告)号：US20230067573A1
公开(公告)日：2023-03-02
申请号：US17459130
申请日：2021-08-27
申请人： Arm Limited
发明人： . ABHISHEK RAJA
IPC分类号： G06F9/22 , G06F9/30
摘要： A predicated vector load micro-operation specifies a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses identified based on the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive. A predetermined type of predicated vector load micro-operation can be issued to the processing circuitry before the predicate operand is determined to meet an availability condition, and if issued in this way memory access circuitry can determine, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition, and if the predetermined condition is unsatisfied, perform a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register.

10. 发明申请

US20230063727A1 Multi-Bit Scan Chain with Error-Bit Generator 有权
公开(公告)号：US20230063727A1
公开(公告)日：2023-03-02
申请号：US17462524
申请日：2021-08-31
申请人： Arm Limited
发明人： Anil Kumar Baratam , Yves Thomas Laplanche
IPC分类号： H03K19/007 , H03K19/173 , H03K19/096
摘要： Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

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