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1. 发明授权

US07987441B2 Method and architecture for power gate switch placement 有权
标题翻译：电源开关放置的方法和架构
公开(公告)号：US07987441B2
公开(公告)日：2011-07-26
申请号：US12538344
申请日：2009-08-10
申请人： Gerald L. Frenkil , Srinivasan Venkatraman
发明人： Gerald L. Frenkil , Srinivasan Venkatraman
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/5077 , H01L27/0207 , H01L27/11807 , H03K19/0016
摘要： A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells.
摘要翻译：设计方法使用逻辑单元行的未占用位置放置电源门或开关单元。可以使用未占用的位置来提供两种类型的这种开关单元，填充开关和密封开关。在一个实施例中，对逻辑单元的虚拟接地电压引用被路由到其相关联的开关单元。因为传统的标准单元设计和放置技术只能在70-80％之间实现放置密度或利用率（即，未占空间占据每行逻辑单元的可用空间的20％到30％之间），通过将功率门单元放入未占用的空间，即使将功率门单元引入到设计中，该方法也不会增加硅的房地产需求。可以应用优化技术来实现功率门单元的适当尺寸和分布，以避免由于功率门单元而导致的性能损失。在一个实施例中，通过选择性地在电源门控逻辑单元之间提供非功率门控逻辑单元来实现细粒度电源门控。

2. 发明授权

US07752578B2 Automatic voltage drop optimization 有权
标题翻译：自动降压优化
公开(公告)号：US07752578B2
公开(公告)日：2010-07-06
申请号：US11551149
申请日：2006-10-19
申请人： David L. Allen , Christopher W. Kapral
发明人： David L. Allen , Christopher W. Kapral
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： To minimize the voltage drops in an electronic circuit, existing instances are moved and decoupling capacitors are automatically inserted according to an algorithm. A model of the voltage drop on a row of gate elements is presented. The model allows for rapid computations of the effect of a particular move or insertion on voltage drop in the circuit.
摘要翻译：为了最小化电子电路中的电压降，现有的实例被移动，并且去耦电容器根据算法自动插入。提出了一排栅极元件上的电压降模型。该模型允许快速计算特定移动或插入对电路中的电压降的影响。

3. 发明授权

US06981230B1 On-chip power-ground inductance modeling using effective self-loop-inductance 有权
标题翻译：使用有效的自环电感的片上电源 - 地电感建模
公开(公告)号：US06981230B1
公开(公告)日：2005-12-27
申请号：US10209081
申请日：2002-07-30
申请人： Shen Lin , Norman Chang , Weize Xie , Richard Chou
发明人： Shen Lin , Norman Chang , Weize Xie , Richard Chou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.
摘要翻译：公开了一种使用其有效自回路电感的片上电源线的高效电感建模方法。不用提取每两根平行线之间的电感耦合，并将这么大数量的电感元件放入电路仿真中，这种技术决定了每个电源或接地线段的有效自环电感，并且只产生一个具有这些有效自感器的电路用于模拟。这种方法大大降低了电路尺寸，并且考虑到电感可以实现全芯片功率 - 地面仿真。

4. 发明授权

US07774728B2 Method that allows flexible evaluation of power-gated circuits 有权
标题翻译：允许灵活评估电源门控电路的方法
公开(公告)号：US07774728B2
公开(公告)日：2010-08-10
申请号：US11150031
申请日：2005-06-10
申请人： Gerald L. Frenkil
发明人： Gerald L. Frenkil
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/5077 , G06F2217/78 , H01L27/0207 , H01L27/11807 , H03K19/0016
摘要： A method and a design automation tool are provided for use in conjunction with designing logic circuits that implement virtual power signals. The method includes providing in a model for each virtual power signal an attribute that distinguishes the virtual power signal from both a logic signal and a power signal. The method also includes one or more circuit analysis, processing and synthesis tool that takes advantage of such an attribute. That is, within the design automation tool, capabilities are provided so that a virtual power signal may be processed in some instances as a logic signal, and at some instance as indistinguishable to a power rail signal or reference.
摘要翻译：提供了一种与设计实现虚拟功率信号的逻辑电路一起使用的方法和设计自动化工具。该方法包括在每个虚拟功率信号的模型中提供将虚拟功率信号与逻辑信号和功率信号两者区分开的属性。该方法还包括利用这种属性的一个或多个电路分析，处理和综合工具。也就是说，在设计自动化工具中，提供了能力，使得虚拟功率信号在某些情况下可以被处理为逻辑信号，并且在某些情况下，与电力轨道信号或参考无法区分。

5. 发明授权

US07750680B2 Automatic extension of clock gating technique to fine-grained power gating 有权
标题翻译：自动延长时钟门控技术到细粒度电源门控
公开(公告)号：US07750680B2
公开(公告)日：2010-07-06
申请号：US11952937
申请日：2007-12-07
申请人： Mahesh Mamidipaka
发明人： Mahesh Mamidipaka
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.
摘要翻译：一种方法延长了时钟选通技术，以提供用于控制降低有源泄漏功率的开关电路的睡眠信号。使用时钟门控技术的这种扩展，实现了细粒度的电源门控。该方法在RTL或门级自动识别可以通过电源门控的逻辑电路。本发明的方法得到可用于时间关键和非时间关键设计的细粒度功率门控的睡眠信号。

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