专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20230133164A1 ENHANCEMENT-TYPE SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20230133164A1
公开(公告)日：2023-05-04
申请号：US17970959
申请日：2022-10-21
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai Cheng
IPC分类号： H01L29/778 , H01L29/20 , H01L29/205 , H01L29/66
摘要： The present disclosure provides an enhancement-type semiconductor structure and a manufacturing method thereof. The enhancement-type semiconductor structure includes: a semiconductor substrate and a heterojunction structure distributed from bottom to top; where the heterojunction structure includes a channel layer close to the semiconductor substrate and a first potential barrier layer far away from the semiconductor substrate; the heterojunction structure includes a gate region, and a source region and a drain region on two sides of the gate region respectively, and an intermediate layer is sandwiched between the channel layer and the first potential barrier layer in the gate region, the intermediate layer is adapted to depolarize the contacted first potential barrier layer.

2. 发明申请

US20230080225A1 ULTRAVIOLET LED AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20230080225A1
公开(公告)日：2023-03-16
申请号：US17802107
申请日：2020-05-13
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai Cheng , Zhuan Liu
IPC分类号： H01L33/06 , H01L33/14 , H01L33/32 , H01L33/00
摘要： This application provides an ultraviolet LED and a manufacturing method thereof. In the manufacturing method, an N-type transition layer is formed above an electron supply layer and/or a P-type transition layer is formed above a hole supply layer, materials of the electron supply layer and the hole supply layer include at least three elements: Al, Ga and N, and materials of the N-type transition layer and the P-type transition layer are GaN; an N electrode is formed on the N-type transition layer, and an ohmic contact is formed between the N-type transition layer and the N electrode; a P electrode is formed on the P-type transition layer, and an ohmic contact is formed between the P-type transition layer and the P electrode.

3. 发明申请

US20230053045A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR 有权
公开(公告)号：US20230053045A1
公开(公告)日：2023-02-16
申请号：US17795481
申请日：2020-03-19
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai Cheng
IPC分类号： H01L29/06 , H01L29/20 , H01L29/66 , H01L29/778 , H01L29/40 , H01L29/417
摘要： The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

4. 发明申请

US20220406918A1 METHOD FOR MANUFACTURING VERTICAL DEVICE 有权
公开(公告)号：US20220406918A1
公开(公告)日：2022-12-22
申请号：US17779398
申请日：2020-11-02
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai Cheng
IPC分类号： H01L29/66 , H01L29/20 , H01L29/872 , H01L21/306
摘要： The present disclosure provides a method for manufacturing vertical device. The method includes: forming a plurality of first grooves in the front side of the N-type heavily doped layer; forming an N-type lightly doped layer in the plurality of first grooves and on the front side of the N-type heavily doped layer; forming second grooves in the N-type lightly doped layer; forming a P-type semiconductor layer in the second grooves and on the front side of the N-type lightly doped layer; planarizing the P-type semiconductor layer; forming a passivation layer on the planarized structure; forming a third groove in the passivation layer, wherein the third groove has a depth equal to a thickness of the passivation layer; and forming a first electrode and a second electrode.

5. 发明申请

US20220238363A1 Graphite Plate 有权
公开(公告)号：US20220238363A1
公开(公告)日：2022-07-28
申请号：US17583646
申请日：2022-01-25
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Peng XIANG
IPC分类号： H01L21/673
摘要： Disclosed is a graphite plate to solve a problem of poor performance uniformity of an epitaxial wafer obtained during carrying on epitaxial growth of material using the graphite plate. A graphite plate includes: a graphite plate body, includes a carrying recess and a recess located on one side of the carrying recess away from a central point of the graphite plate body; and a stopper, which is embedded in the recess in a matching manner, and the stopper protrudes from the bottom surface of the carrying recess to form a limiting structure.

6. 发明申请

US20220199781A1 ENHANCEMENT-MODE SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20220199781A1
公开(公告)日：2022-06-23
申请号：US17554186
申请日：2021-12-17
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai CHENG
IPC分类号： H01L29/20 , H01L29/10 , H01L29/205 , H01L29/778
摘要： Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type nitride semiconductor layer and an n-type nitride semiconductor layer formed on the substrate in sequence, the p-type nitride semiconductor layer having a first protruding structure at a gate region of the p-type nitride semiconductor layer; the n-type nitride semiconductor layer having a first through hole corresponding to the first protruding structure, exposing the gate region of the p-type nitride semiconductor layer; a channel layer conformally disposed on the n-type semiconductor layer and the first protruding structure; a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids impurities and defects brought to the channel layer and the barrier layer.

7. 发明授权

US11361963B2 Semiconductor structure and method for manufacturing the same 有权
公开(公告)号：US11361963B2
公开(公告)日：2022-06-14
申请号：US16931612
申请日：2020-07-17
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai Cheng
IPC分类号： H01L21/02 , H01L29/06
摘要： A semiconductor structure includes a substrate; a nucleation layer located above the substrate; and a metal nitride thin film located between the nucleation layer and the substrate. A diffusion of atoms in a material of the substrate is suppressed by depositing the metal nitride thin film between the substrate and the nucleation layer, so that a thickness of the nucleation layer is significantly reduced, and a total thermal resistance of the semiconductor structure is reduced.

8. 发明申请

US20220084821A1 Methods Of Manufacturing Vertical Device 有权
公开(公告)号：US20220084821A1
公开(公告)日：2022-03-17
申请号：US17599668
申请日：2019-09-12
申请人： Enkris Semiconductor, Inc.
发明人： Kai Cheng
IPC分类号： H01L21/02 , H01L21/321 , H01L29/812
摘要： The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate (10) is etched from a front surface (10a) to form a trench (101). Then, a P-type semiconductor layer (11) and an N-type semiconductor layer (12) are sequentially formed on a bottom wall and side walls of the trench (101) and the front surface (10a) of the semiconductor substrate. The trench (101) is partially filled with the P-type semiconductor layer (11). Thereafter, the N-type semiconductor layer (12) and the P-type semiconductor layer (11) are planarized, and the P-type semiconductor layer (11) and the N-type semiconductor layer (12) in the trench (101) are retained. Next, a gate structure (13) is formed at a gate area of the front surface (10a) of the semiconductor substrate, a source electrode (14) is formed on two sides of the gate structure (13), and a drain electrode (15) is formed on a rear surface (10b) of the semiconductor substrate respectively. Etching the N-type semiconductor layer (12) and the P-type semiconductor layer (11) is avoided to make the gate structure (13), thereby avoiding that the control capability of the gate structure (13) deviates from a pre-designed control capability due to a difficulty in precise control over an etching depth. In this way, the performance of the vertical device can be precisely controlled through a manufacturing process.

9. 发明申请

US20220069113A1 SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOF 有权
公开(公告)号：US20220069113A1
公开(公告)日：2022-03-03
申请号：US17276809
申请日：2019-11-26
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai CHENG
IPC分类号： H01L29/778 , H01L29/20 , H01L29/66
摘要： The present disclosure provides semiconductor structures and methods of manufacturing the same. In the semiconductor structure, an in-situ insulating layer is formed on a heterojunction, a groove is provided in the in-situ insulating layer, and a transition layer is provided in the groove and on the in-situ insulating layer. A P-type semiconductor layer is provided on the transition layer in a gate region. The P-type semiconductor layer does not fully fill the groove.

10. 发明申请

US20220005728A1 WAFER SUSCEPTOR AND CHEMICAL VAPOR DEPOSITION APPARATUS 有权
公开(公告)号：US20220005728A1
公开(公告)日：2022-01-06
申请号：US17478638
申请日：2021-09-17
申请人： ENKRIS SEMICONDUCTOR, INC.
发明人： Kai LIU , Kai CHENG
IPC分类号： H01L21/687 , C23C16/458
摘要： Disclosed are a wafer susceptor and a chemical vapor deposition apparatus, which solve a problem of a decrease in yield due to uneven wavelength of deposited epitaxial material caused by uneven heating during a wafer manufacturing process. The wafer susceptor includes: a wafer carrying groove; and two convex structures disposed at the bottom of the wafer carrying groove.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式