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1. 发明申请

US20230094795A1 REEL-TO-REEL SURFACE PRESS APPARATUS 有权
公开(公告)号：US20230094795A1
公开(公告)日：2023-03-30
申请号：US17818516
申请日：2022-08-09
申请人： HAESUNG DS CO., LTD.
发明人： Yong Nam Kim , Jae Hoon Jang
IPC分类号： B65H18/10 , B65H23/188 , B65H18/12 , B65H23/032
摘要： Disclosed in a reel-to-reel surface press apparatus. The reel-to-reel surface press apparatus includes an uncoiler and a recoiler, both transferring a component in a reel-to-reel method, a press disposed between the uncoiler and the recoiler, comprising a press plate pressing the component, and having a plurality of reference holes at an equal pitch along an edge of the press plate, a feeder disposed at the rear of the uncoiler and moving the component, and a controller configured to control the component to be transferred based on at least any one of the plurality of reference holes.

2. 发明申请

US20230080101A1 SEMICONDUCTOR PACKAGE SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20230080101A1
公开(公告)日：2023-03-16
申请号：US17930112
申请日：2022-09-07
申请人： HAESUNG DS CO., LTD.
发明人： Dong Jin YOON , Sung Il KANG , In Seob BAE , Seok Kyu SEO , Dong Young PYEON
IPC分类号： H01L23/12 , H01L23/00 , H01L21/48 , H01L23/053
摘要： Provided are a semiconductor package substrate, a method of manufacturing the semiconductor package substrate, and a semiconductor package. According to one embodiment of the present disclosure, a semiconductor package substrate includes a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, including a circuit pattern and a conductive material; a first resin arranged in the first trench; and a second resin arranged in the second trench and the third trench, wherein the second trench exposes at least a part of the first resin.

3. 发明申请

US20220285251A1 SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20220285251A1
公开(公告)日：2022-09-08
申请号：US17653763
申请日：2022-03-07
申请人： HAESUNG DS CO., LTD.
发明人： Wonbin Kim , Sung Il Kang , In Seob Bae , Dong Jin Yoon
IPC分类号： H01L23/495 , H01L23/00 , H01L21/48
摘要： A semiconductor package substrate and a method of manufacturing the same are provided. The semiconductor package substrate includes: a base layer including a conductive material, having a first surface and a second surface opposite the first surface, and having a first groove or first trench in the first surface and a second groove or second trench in the second surface; a first resin buried in the first groove or first trench in the first surface of the base layer; and a groove in at least one corner of the first surface of the base layer and having a depth based on the first surface is 1/2 or more of a thickness of the base layer.

4. 发明申请

US20210098268A1 METHOD OF FABRICATING CARRIER FOR WAFER LEVEL PACKAGE BY USING LEAD FRAME 有权
公开(公告)号：US20210098268A1
公开(公告)日：2021-04-01
申请号：US16854704
申请日：2020-04-21
申请人： HAESUNG DS CO., LTD.
发明人： Dong Young PYEON , Sung Il KANG , Jong Hoe KU , In Seob BAE
IPC分类号： H01L21/48
摘要： According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.

5. 发明申请

US20190057930A1 SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING SAME 审中-公开
公开(公告)号：US20190057930A1
公开(公告)日：2019-02-21
申请号：US16079965
申请日：2016-11-10
申请人： HAESUNG DS CO., LTD.
发明人： In Seob BAE , Sung Il KANG
IPC分类号： H01L23/495 , H01L23/00 , H01L21/48
摘要： A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

6. 发明授权

US09299588B2 Method of manufacturing lead frame 有权
标题翻译：制造引线框架的方法
公开(公告)号：US09299588B2
公开(公告)日：2016-03-29
申请号：US14182783
申请日：2014-02-18
申请人： HAESUNG DS CO., LTD.
发明人： Jeung-Il Kim
IPC分类号： H01L21/00 , H01L21/48 , H01L23/495 , H01L23/31
CPC分类号： H01L21/4842 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L2224/48247
摘要： There is provided a method of manufacturing a lead frame, the method including: preparing a lead frame raw material; forming openings in the lead frame raw material so that the lead frame material includes: a die pad; a die pad supporting portion supporting the die pad; a rail portion supporting the die pad supporting portion; a lead supporting portion having both ends fixed to the die pad supporting portion; and a plurality of leads having a first end connected to the rail portion and a second end connected to the lead supporting portion; plating the lead frame raw material having the openings with a plating layer; and removing the lead supporting portion.
摘要翻译：提供一种制造引线框架的方法，该方法包括：制备引线框架原料; 在引线框架原材料中形成开口，使得引线框架材料包括：芯片焊盘; 支撑所述管芯焊盘的管芯焊盘支撑部; 支撑所述管芯焊盘支撑部的轨道部分; 引线支撑部分，其两端固定到管芯焊盘支撑部分; 以及多个引线，其具有连接到所述导轨部分的第一端和连接到所述引线支撑部分的第二端; 用镀层电镀具有开口的引线框架原材料; 并且移除引线支撑部分。

7. 发明授权

US09173300B2 Method of manufacturing printed circuit board 有权
标题翻译：制造印刷电路板的方法
公开(公告)号：US09173300B2
公开(公告)日：2015-10-27
申请号：US13603959
申请日：2012-09-05
申请人： Jeong-Hoon Seol , Youn-Kwon Jung , Sang-Kun Kim
发明人： Jeong-Hoon Seol , Youn-Kwon Jung , Sang-Kun Kim
IPC分类号： H05K3/36 , H05K3/00 , H05K3/42
CPC分类号： H05K3/0094 , H05K3/427 , H05K2201/0959
摘要： A method of manufacturing a printed circuit board (PCB) and the PCB are provided. The method includes: filling a resin in a via-hole formed at a substrate from one surface side of the substrate; emitting light for a predetermined period of time to the resin filled in the via-hole from the other surface side of the substrate; and applying another resin on the other surface of the substrate.
摘要翻译：提供了制造印刷电路板（PCB）和PCB的方法。该方法包括：从基板的一个表面侧将树脂填充在形成在基板上的通孔中; 从衬底的另一个表面侧向填充在通孔中的树脂发光预定时间; 以及在所述基板的另一表面上施加另一树脂。

8. 发明授权

US09171789B2 Lead frame, semiconductor package including the lead frame, and method of manufacturing the lead frame 有权
标题翻译：引线框架，包括引线框架的半导体封装以及引线框架的制造方法
公开(公告)号：US09171789B2
公开(公告)日：2015-10-27
申请号：US13958980
申请日：2013-08-05
申请人： HAESUNG DS CO., LTD.
发明人： Dong-Il Shin , In-Seob Bae , Se-Chuel Park
IPC分类号： H01L23/495 , C25D5/12 , C25D5/02 , C25D17/00 , C25D5/34
CPC分类号： H01L23/49582 , C25D5/022 , C25D5/12 , C25D5/34 , C25D17/00 , H01L23/49548 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48464 , H01L2224/48465 , H01L2924/00014 , H01L2924/00
摘要： There is provided a lead frame including a plurality of plating layers formed on both an upper surface and a lower surface of a base material including a metal, wherein an upper outermost plating layer of an upper part of the lead frame is a silver plating layer including silver, and a lower outermost plating layer of a lower part of the lead frame is a gold plating layer including gold.
摘要翻译：提供了一种引线框架，其包括形成在包括金属的基材的上表面和下表面上的多个镀层，其中引线框架的上部的最外侧镀层是银镀层，包括银，并且引线框架的下部的最外面的镀层是包含金的镀金层。

9. 发明申请

US20230102887A1 LEAD FRAME 有权
公开(公告)号：US20230102887A1
公开(公告)日：2023-03-30
申请号：US17930537
申请日：2022-09-08
申请人： HAESUNG DS CO., LTD.
发明人： Dong Jin Yoon , Sung Il Kang , In Seob BAE , Seok Kyu SEO , Dong Young Pyeon
IPC分类号： H01L23/495 , H01L21/56
摘要： A lead frame includes: leads; and a dambar arranged between the leads and connecting the leads to each other, wherein each of the leads includes: a lower lead groove formed in a first surface for a wettable flank structure; and an upper lead groove formed in a second surface opposite the first surface and aligned with the lower lead groove in a thickness direction, wherein in a sawing process, a portion of the lead between the lower lead groove and the upper lead groove is at least partially removed.

10. 发明申请

US20220082454A1 SENSOR PACKAGE AND SENSOR PACKAGE MODULE INCLUDING THE SAME 有权
公开(公告)号：US20220082454A1
公开(公告)日：2022-03-17
申请号：US17531570
申请日：2021-11-19
申请人： HAESUNG DS CO., LTD.
发明人： Jin Woo LEE
IPC分类号： G01K11/26 , G01K1/08 , H01L23/48
摘要： Provided are a sensor package and a sensor package module. The sensor package includes: a substrate including a sensing area; a terminal portion disposed on a side of the sensing area of the substrate and including at least one terminal connected to the outside; a first outer wall disposed on the substrate and including a main wall surrounding at least some outer portions of the sensing area; at least one wire patterned and disposed on the substrate and configured to connect the sensing area and the terminal portion to each other; and a cover disposed on the first outer wall to correspond to the sensing area. Part of the main wall is disposed between the sensing area and the terminal portion, and the main wall includes an opening through which the at least one wire passes.

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