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1. 发明授权

US11075290B2 Power semiconductor device having a cross-trench arrangement 有权
公开(公告)号：US11075290B2
公开(公告)日：2021-07-27
申请号：US16409454
申请日：2019-05-10
申请人： Infineon Technologies AG , Infineon Technologies Dresden GmbH & Co. KG
发明人： Matteo Dainese , Alexander Philippou , Markus Bina , Ingo Dirnstorfer , Erich Griebl , Christian Jaeger , Johannes Georg Laven , Caspar Leendertz , Frank Dieter Pfirsch
IPC分类号： H01L29/00 , H01L29/739 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/66 , H01L29/423
摘要： A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.

2. 发明申请

US20150280696A1 CIRCUIT FOR COMMON MODE REMOVAL FOR DC-COUPLED FRONT-END CIRCUITS 有权
标题翻译：用于直流耦合前端电路的通用模式拆除电路
公开(公告)号：US20150280696A1
公开(公告)日：2015-10-01
申请号：US14225003
申请日：2014-03-25
申请人： Infineon Technologies Austria AG
发明人： Giuseppe Bernacchia , Cha-fu Tsai
IPC分类号： H03K5/007
CPC分类号： H03K5/007
摘要： In one example, a method includes receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first differential signal includes a first common mode voltage; receiving a second common mode voltage. The method further includes determining, by a circuit, a second differential signal including a third voltage signal and a fourth voltage signal, wherein a difference between the third voltage signal and the fourth voltage signal is based on a difference between the first voltage signal and the second voltage signal, wherein the second differential signal includes the second common mode voltage. The method further includes outputting, substantially continuously, the second differential signal.
摘要翻译：在一个示例中，一种方法包括接收包括第一电压信号和第二电压信号的第一差分信号，其中第一差分信号包括第一共模电压; 接收第二共模电压。该方法还包括通过电路确定包括第三电压信号和第四电压信号的第二差分信号，其中第三电压信号和第四电压信号之间的差是基于第一电压信号和第四电压信号之间的差值第二电压信号，其中第二差分信号包括第二共模电压。该方法还包括基本连续地输出第二差分信号。

3. 发明授权

US07863201B2 Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance 有权
标题翻译：形成具有低接触电阻的硅化源极/漏极触点的场效应晶体管的方法
公开(公告)号：US07863201B2
公开(公告)日：2011-01-04
申请号：US12402816
申请日：2009-03-12
申请人： Yong-Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
发明人： Yong-Kuk Jeong , Bong-Seok Suh , Dong-Hee Yu , Oh-Jung Kwon , Seong-Dong Kim , O Sung Kwon
IPC分类号： H01L21/31 , H01L21/469 , H01L21/00
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L29/6659 , H01L29/7833
摘要： Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
摘要翻译：根据本发明的实施例的形成集成电路器件的方法包括在半导体衬底中形成具有P型源极和漏极区域的PMOS晶体管，然后在源极和漏极区域上形成扩散阻挡层。在扩散阻挡层的与源区和漏区相对延伸的至少一部分上沉积氮化硅层。通过将氮化硅层暴露于紫外线（UV）辐射，从沉积的氮化硅层去除氢。这种氢的去除可以用于增加场效应晶体管的沟道区域中的拉伸应力。该UV辐射步骤之后可以对第一和第二氮化硅层进行构图以暴露出源区和漏区，然后直接在暴露的源极和漏极区上形成硅化物接触层。

4. 发明授权

US07796699B2 Allocating data between tones 有权
标题翻译：在色调之间分配数据
公开(公告)号：US07796699B2
公开(公告)日：2010-09-14
申请号：US12324421
申请日：2008-11-26
申请人： Raj Kumar Jain , Sim Hak Keong
发明人： Raj Kumar Jain , Sim Hak Keong
IPC分类号： H04K1/10
CPC分类号： H04L27/2628 , H04L27/2633
摘要： A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are associated into groups 10, 11, and tone ordering, gain selection, and/or bit swapping within the processing system are done within the members of a group 10, 11. This idea is applicable both to tone ordering etc., following the training stage, and also to the dynamic configuration changes subsequently, for example, bit swapping. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the memory requirements of the encoder and decoder.
摘要翻译：提出了一种新的协议，用于通过诸如电话线的线路传输数据。信号的音调被关联到组10,11中，并且处理系统内的音调排序，增益选择和/或位交换在组10,11的成员内完成。这个想法适用于音调排序等在训练阶段之后，以及随后的动态配置变化，例如位交换。数字编码和解码的计算成本降低（与处理给定方向的所有音调相当），本发明可以显着降低编码器和解码器的存储器要求。

5. 发明授权

US07205195B2 Method for fabricating NROM memory cells with trench transistors 有权
标题翻译：用沟槽晶体管制造NROM存储单元的方法
公开(公告)号：US07205195B2
公开(公告)日：2007-04-17
申请号：US11006049
申请日：2004-12-07
申请人： Christoph Kleint , Christoph Ludwig , Josef Willer , Joachim Deppe
发明人： Christoph Kleint , Christoph Ludwig , Josef Willer , Joachim Deppe
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).
摘要翻译：在沟槽被蚀刻到半导体材料之前，将导电位线层施加并图案化成彼此平行布置的部分，在这种情况下，在位线层（3,4）的图案化之后并且在蚀刻引入注入用于限定结的位置，或者在用于源极/漏极区的n + H +型阱（19）的注入之后，位线层（3,4）使用布置在半导体本体（1）上的蚀刻停止层（2）进行图案化。

6. 发明授权

US07075137B2 Semiconductor memory having charge trapping memory cells 失效
标题翻译：具有电荷捕获存储单元的半导体存储器
公开(公告)号：US07075137B2
公开(公告)日：2006-07-11
申请号：US10890803
申请日：2004-07-14
申请人： Josef Willer , Christoph Ludwig , Joachim Deppe
发明人： Josef Willer , Christoph Ludwig , Joachim Deppe
IPC分类号： H01L27/108
CPC分类号： H01L27/11568 , H01L27/115
摘要： In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations (7) that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines (41, 42) may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.
摘要翻译：在具有与字线（2）并行存在的互连（6）的虚拟接地的电荷捕获存储器架构中，并行于位线（4）的STI隔离（1），提供STI隔离（ 7）被分割成切片。而不是这样，存在于位线下方的互连可以被省略，或者两个相互相邻的位线（41,42）可以以使得它们之间存在的存储晶体管仅在虚拟模式中操作的方式被布线。

7. 发明授权

US06996479B2 Method and apparatus for measuring and controlling the water content of a water-containing liquid mixture 失效
公开(公告)号：US06996479B2
公开(公告)日：2006-02-07
申请号：US10403878
申请日：2003-03-31
申请人： Stefan Ottow , Martin Welzel , Dan Wissel
发明人： Stefan Ottow , Martin Welzel , Dan Wissel
IPC分类号： G06F19/00
CPC分类号： G01N25/56 , G01N25/142 , H01L21/31111
摘要： An apparatus for measuring the water content of a water-containing liquid mixture contained in a tight chemistry tank includes a heating device for controlling the temperature of the liquid mixture to a temperature near the boiling point of the liquid mixture, a cooling medium system disposed at the top of the tight chemistry tank having a cooling medium inlet and a cooling medium outlet, a temperature measurement system for determining the temperature difference between the cooling medium inlet and outlet, and a computing device for calculating the water content of the liquid mixture from the temperature difference. Also provided is a tank for supplying water to the liquid mixture, and a control system for adjusting the amount of water supplied from the tank based upon the water content measured by the measuring apparatus. Also provided is a method for measure the water content.

8. 发明授权

US11610986B2 Power semiconductor switch having a cross-trench structure 有权
公开(公告)号：US11610986B2
公开(公告)日：2023-03-21
申请号：US17350505
申请日：2021-06-17
申请人： Infineon Technologies AG , Infineon Technologies Dresden GmbH & Co. KG
发明人： Matteo Dainese , Alexander Philippou , Markus Beninger-Bina , Ingo Dirnstorfer , Erich Griebl , Christian Jaeger , Johannes Georg Laven , Caspar Leendertz , Frank Dieter Pfirsch
IPC分类号： H01L29/00 , H01L29/739 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/66 , H01L29/423
摘要： A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

9. 发明授权

US07670901B2 Method of fabricating a bottle trench and a bottle trench capacitor 失效
标题翻译：制造瓶沟槽和瓶槽电容器的方法
公开(公告)号：US07670901B2
公开(公告)日：2010-03-02
申请号：US12033984
申请日：2008-02-20
申请人： Oh-Jung Kwon , Kenneth T. Settlemyer, Jr. , Ravikumar Ramachandran , Min-Soo Kim
发明人： Oh-Jung Kwon , Kenneth T. Settlemyer, Jr. , Ravikumar Ramachandran , Min-Soo Kim
IPC分类号： H01L21/762
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.
摘要翻译：制造瓶沟槽和瓶沟电容器的方法。该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。

10. 发明授权

US07427548B2 Method for producing charge-trapping memory cell arrays 有权
标题翻译：电荷俘获存储单元阵列的制造方法
公开(公告)号：US07427548B2
公开(公告)日：2008-09-23
申请号：US11170187
申请日：2005-06-29
申请人： Stephan Riedel , Stefano Parascandola
发明人： Stephan Riedel , Stefano Parascandola
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling (7) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks (8) are formed.
摘要翻译：在硅衬底（1）的主表面上施加包括下约束层（2），电荷俘获层（3）和上限制层（4）的存储层序列。通过光刻步骤，蚀刻彼此间隔一定距离的平行沟槽，以界定有效面积。沟槽填充（7）通过介电材料的生长或沉积或通过基底材料的选择性氧化来施加。在去除外围区域中的电荷捕获层序列并且为寻址电路的晶体管提供的栅极电介质材料的沉积形成字线叠层（8）之后。

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