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1. 发明授权

US10534619B2 Memory management system with multiple boot devices and method of operation thereof 有权
公开(公告)号：US10534619B2
公开(公告)日：2020-01-14
申请号：US15055448
申请日：2016-02-26
申请人： SMART Modular Technologies, Inc.
发明人： Robert T. Frey
IPC分类号： G06F9/4401
摘要： A memory management system, and method of operation thereof, includes: a primary device of a resilient storage module configured as a boot device for booting a computer system; an operational status received from the computer system; a secondary device of the resilient storage module configured as the boot device based on the operational status indicating a non-operational state; and a memory module controller of the resilient storage module for initiating a reboot operation using the secondary device as the boot device.

2. 发明授权

US10529688B1 Integrated circuit device system with elevated configuration and method of manufacture thereof 有权
公开(公告)号：US10529688B1
公开(公告)日：2020-01-07
申请号：US15462885
申请日：2017-03-19
申请人： SMART Modular Technologies, Inc.
发明人： Satyanarayan Shivkumar Iyer , Reuben J. Chang , Victor Mahran
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A system and method of manufacture of an integrated circuit device system includes mounting a first elevated device on a first riser positioned adjacent to a base device. The first elevated device includes a first device overhang that extends over the base device. A second elevated device can be mounted on a second riser adjacent to the first riser to allow the attachment of a second elevated device mounted above the first elevated device to achieve higher component densities.

3. 发明授权

US10474362B2 Flash-based block storage system with trimmed space management and method of operation thereof 有权
公开(公告)号：US10474362B2
公开(公告)日：2019-11-12
申请号：US15294678
申请日：2016-10-14
申请人： SMART Modular Technologies, Inc.
发明人： Victor Y. Tsai , Robert Fillion
IPC分类号： G06F3/06 , G06F12/02
摘要： Approaches, techniques, and mechanisms are disclosed for a method of operation of a Flash-based block storage system including: transferring a first data to a logical block address; storing the first data in a physical block, of a storage array, associated with the logical block address; receiving a trim command for the logical block address; establishing a reserved physical block associated with the logical block address of the trim command; transferring second data for writing to the logical block address of the trim command; releasing the reserved physical block associated with the logical block address; and writing the second data to the logical block address.

4. 发明授权

US10409754B2 Interconnected memory system and method of operation thereof 有权
公开(公告)号：US10409754B2
公开(公告)日：2019-09-10
申请号：US15141757
申请日：2016-04-28
申请人： SMART Modular Technologies, Inc.
发明人： Rajesh Ananthanarayanan
IPC分类号： G06F13/38 , G06F13/40 , G06F3/06
摘要： An interconnected memory system, and a method of operation thereof, including: a first discrete unit having a first unit processor and first unit memory module; a high-speed interconnect connected directly to the first unit memory module; and a second discrete unit having a second unit processor and a second unit memory module, the second unit memory module connected to the first unit memory module through the high-speed interconnect for utilizing the first unit memory module and the second unit memory module with the first unit processor.

5. 发明授权

US09939855B2 Extended capacity memory system with load relieved memory and method of manufacture thereof 有权
公开(公告)号：US09939855B2
公开(公告)日：2018-04-10
申请号：US14942787
申请日：2015-11-16
申请人： SMART Modular Technologies, Inc.
发明人： Victor Mahran , Robert S. Pauley, Jr.
IPC分类号： G06F1/18 , H05K7/14 , H05K1/14 , G06F1/20 , G11C5/02 , H05K1/02
CPC分类号： G06F1/185 , G06F1/20 , G11C5/025 , H05K1/0209 , H05K1/144 , H05K1/145 , H05K7/1431 , H05K2201/042 , H05K2201/10159 , H05K2201/10303 , H05K2201/10378 , H05K2201/10409 , Y10T29/4913
摘要： A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.

6. 发明授权

US09754634B2 Memory management system with power source and method of manufacture thereof 有权
公开(公告)号：US09754634B2
公开(公告)日：2017-09-05
申请号：US13303863
申请日：2011-11-23
申请人： Jinying Shen , Robert Tower Frey , Kelvin Marino , Joshua Harris Brooks
发明人： Jinying Shen , Robert Tower Frey , Kelvin Marino , Joshua Harris Brooks
IPC分类号： G11C5/14
CPC分类号： G11C5/141 , Y10T29/49117
摘要： A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.

7. 发明授权

US09424188B2 Non-volatile memory packaging system with caching and method of operation thereof 有权
标题翻译：具有缓存的非易失性存储器封装系统及其操作方法
公开(公告)号：US09424188B2
公开(公告)日：2016-08-23
申请号：US13303818
申请日：2011-11-23
申请人： Mike H. Amidi , Michael Rubino , Alessandro Fin
发明人： Mike H. Amidi , Michael Rubino , Alessandro Fin
IPC分类号： G06F12/00 , G06F12/08 , G06F13/16 , G06F3/06
CPC分类号： G06F12/0804 , G06F3/0661 , G06F13/16 , G06F2212/2022 , G06F2212/3042
摘要： A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface.
摘要翻译：非易失性存储器封装系统的操作方法包括：寻址具有系统接口的集成电路封装; 通过系统接口访问集成电路封装中的模块控制器; 通过模块控制器访问集成电路封装中的随机存取存储器，用于存储来自系统接口的数据; 在模块控制器的集成电路封装中写入来自随机存取存储器的数据的非易失性存储器; 以及由模块控制器监视地址查找寄存器，用于通过系统接口从非易失性存储器或随机存取存储器读取数据。

8. 发明申请

US20130083473A1 EXTENDED CAPACITY MEMORY SYSTEM WITH LOAD RELIEVED MEMORY AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有负载恢复存储器的扩展容量存储器系统及其制造方法
公开(公告)号：US20130083473A1
公开(公告)日：2013-04-04
申请号：US13633074
申请日：2012-10-01
申请人： SMART MODULAR TECHNOLOGIES, INC.
发明人： Victor Mahran , Robert S. Pauley, JR.
IPC分类号： H05K7/10 , H05K3/30
CPC分类号： G06F1/185 , G06F1/20 , G11C5/025 , H05K1/0209 , H05K1/144 , H05K1/145 , H05K7/1431 , H05K2201/042 , H05K2201/10159 , H05K2201/10303 , H05K2201/10378 , H05K2201/10409 , Y10T29/4913
摘要： A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof
摘要翻译：一种制造增强容量存储器系统的方法包括：提供具有存储器模块和耦合到存储器模块的集成存储器缓冲器的双列直插存储器模块载体; 将具有辅助存储器模块的存储器扩展板耦合到双列直插式存储器模块载体，包括附接桥式变压器; 并且提供耦合到集成存储器缓冲器的系统接口连接器和用于控制存储器模块，辅助存储器模块或其组合的桥接转换器

9. 发明授权

US08156252B2 Apparatus and method for block-based data striping to solid-state memory modules with optional data format protocol translation 有权
标题翻译：用于基于块的数据条带化到具有可选数据格式协议转换的固态存储器模块的装置和方法
公开(公告)号：US08156252B2
公开(公告)日：2012-04-10
申请号：US12702998
申请日：2010-02-09
申请人： Ryan McDaniel
发明人： Ryan McDaniel
IPC分类号： G06F3/00
CPC分类号： G06F13/4027
摘要： In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.
摘要翻译：在各种实施例中，提供了用于数据条带化到闪速存储器的选项。在一个实施例中，提供了一种装置。该装置包括SATA到ATA桥，连接到SATA到ATA桥的ATA到USB桥，以及耦合到ATA到USB桥的USB接口。该装置还包括耦合到USB接口的第一FLASH存储器控制器。该装置还包括耦合到第一FLASH存储器控制器的第一FLASH存储器模块。该装置还包括耦合到USB接口的第二闪速存储器控制器和耦合到第二闪速存储器控制器的第二闪速存储器模块。一种用于将数据分离到多个读取或写入通道的数据的方法。

10. 发明申请

US20080155378A1 Memory modules with error detection and correction 有权
标题翻译：具有错误检测和校正的内存模块
公开(公告)号：US20080155378A1
公开(公告)日：2008-06-26
申请号：US11643100
申请日：2006-12-21
申请人： Hossein Amidi
发明人： Hossein Amidi
IPC分类号： H03M13/00
CPC分类号： H03M13/03 , H03M13/09 , H03M13/091 , H03M13/3776
摘要： A memory module having error detection and correction mechanisms is disclosed. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal.
摘要翻译：公开了一种具有错误检测和校正机制的存储器模块。存储器模块包括布置在阵列中的多个存储器件和连接到存储器件的缓冲器件。该缓冲装置包括用于同步并缓冲多个输入信号到存储装置的寄存器模块，用于检测输入信号的错误的错误检测模块，以及用于存储输入信号的副本并发送存储的副本的输入信号作为输出信号。

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