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1. 发明授权

US11635487B2 Method and apparatus for controlling radar transmission based on comparing received radio waves 有权
公开(公告)号：US11635487B2
公开(公告)日：2023-04-25
申请号：US16857899
申请日：2020-04-24
申请人： SOCIONEXT INC.
发明人： Joji Hayashi
IPC分类号： G01S7/02 , G01S7/28 , G01S7/292 , G01S13/28 , H04W72/541
摘要： A method for controlling a radar apparatus that detects an object using frequency modulation includes: performing first reception of a radio wave in a state where transmission of a radio wave for detecting the object is stopped, to obtain a first reception signal; performing second reception of a radio wave in a state where the transmission of the radio wave is stopped, to obtain a second reception signal, after the performing of the first reception; acquiring a strength of a difference signal between the first reception signal and the second reception signal; comparing the strength with a threshold value; and starting the transmission of the radio wave in a case where the strength is equal to or less than the first threshold value in the comparison.

2. 发明授权

US11626386B2 Semiconductor integrated circuit device and semiconductor package structure 有权
公开(公告)号：US11626386B2
公开(公告)日：2023-04-11
申请号：US17206257
申请日：2021-03-19
申请人： SOCIONEXT INC.
发明人： Atsushi Okamoto , Hirotaka Takeno , Wenzhen Wang
IPC分类号： H01L23/50 , H01L25/065 , H01L23/538 , H01L27/088
摘要： A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

3. 发明申请

US20230095506A1 AMPLIFIER CIRCUIT, DIFFERENTIAL AMPLIFIER CIRCUIT, RECEPTION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
公开(公告)号：US20230095506A1
公开(公告)日：2023-03-30
申请号：US18061757
申请日：2022-12-05
申请人： Socionext Inc.
发明人： Ryoichiro NAKAMURA , Masahiro KUDO
IPC分类号： H03F3/45 , H03F1/08
摘要： An amplifier circuit according to an embodiment includes a first circuit, a second circuit, and a third circuit. The first circuit includes a first transistor connected between an input node through which an input current flows and a reference potential node. The first transistor has a gate electrode connected to the input node. The second circuit includes a low-pass filter circuit and a second transistor connected in parallel to the first transistor between the input node and the reference potential node. The second transistor has a gate electrode connected to the gate electrode of the first transistor via the low-pass filter circuit. The third circuit includes a third transistor connected between an output node through which an output current flows and the reference potential node, the third circuit having a gate electrode connected to the gate electrode of the first transistor.

4. 发明申请

US20230058077A1 ADC CIRCUITRY COMPRISING COMPENSATION CIRCUITRY 有权
公开(公告)号：US20230058077A1
公开(公告)日：2023-02-23
申请号：US17880417
申请日：2022-08-03
申请人： Socionext Inc.
发明人： Sandeep SANTHOSH KUMAR , Jayaraman KUMAR , Armin JALILI SEBARDAN , Martin WILSON
IPC分类号： H03M1/06
摘要： Analogue-to-digital converter, ADC, circuitry comprising: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry comprising at least one compensation capacitor and configured, in a precharge operation prior to the subconversion operation, to connect the at least one compensation capacitor so that the at least one compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the at least one compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry compensates for the charge drawn from the first voltage reference, REF1, by the successive-approximation circuitry.

5. 发明申请

US20230027616A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
公开(公告)号：US20230027616A1
公开(公告)日：2023-01-26
申请号：US17945800
申请日：2022-09-15
申请人： Socionext Inc.
发明人： Toshio HINO
IPC分类号： H01L27/02 , H01L23/528
摘要： A semiconductor integrated circuit device includes a clock buffer cell that is a standard cell transmitting a clock signal. The clock buffer cell has an input terminal and an output terminal. A first metal interconnect including the output terminal is located in a layer above a second metal interconnect including the input terminal and greater in width than the second metal interconnect.

6. 发明申请

US20220415885A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
公开(公告)号：US20220415885A1
公开(公告)日：2022-12-29
申请号：US17902537
申请日：2022-09-02
申请人： Socionext Inc.
发明人： Isaya SOBUE
IPC分类号： H01L27/07 , H01L29/06 , H01L29/786 , H01L29/775 , H01L23/528
摘要： A layout structure of a capacitive element using forksheet FETs is provided. A capacitive structure constituting the capacitive element includes: a first transistor having a first nanosheet extending in the X direction and a first gate interconnect extending in the Y direction and surrounding the periphery of the first nanosheet; and a second transistor having a second nanosheet extending in the X direction and a second gate interconnect extending in the Y direction and surrounding the periphery of the second nanosheet. The face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and the face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect.

7. 发明申请

US20220407513A1 SAMPLING SWITCH CIRCUITS 有权
公开(公告)号：US20220407513A1
公开(公告)日：2022-12-22
申请号：US17834653
申请日：2022-06-07
申请人： SOCIONEXT INC
发明人： Vlad CRETU , Masahiro KUDO
IPC分类号： H03K17/687
摘要： A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.

8. 发明申请

US20220398693A1 COLOR IMAGE INPAINTING METHOD AND NEURAL NETWORK TRAINING METHOD 有权
公开(公告)号：US20220398693A1
公开(公告)日：2022-12-15
申请号：US17891687
申请日：2022-08-19
申请人： Socionext Inc.
发明人： Yukihiro SASAGAWA
IPC分类号： G06T5/00
摘要： A color image inpainting method includes: obtaining a color image of an object to be recognized, the color image including a missing portion where at least part of image information is missing; obtaining an infrared image of the object; identifying the missing portion in the color image; and inpainting the missing portion in the color image identified in the identifying. The inpainting includes inpainting the missing portion by using information which is obtained from the infrared image and corresponds to the missing portion to obtain an inpainted color image of the object.

9. 发明申请

US20220310631A1 SEMICONDUCTOR STORAGE DEVICE 有权
公开(公告)号：US20220310631A1
公开(公告)日：2022-09-29
申请号：US17840079
申请日：2022-06-14
申请人： Socionext Inc.
发明人： Masanobu HIROSE
IPC分类号： H01L27/11 , H01L29/06 , H01L29/423 , H01L29/786
摘要： Nanosheets 21a to 21d are formed in line in this order in the X direction, and nanosheets 21e to 21h are formed in line in this order in the X direction. Faces of the nanosheets 21c, 21f, and 21g on the first side as one of the opposite sides in the X direction are exposed from gate interconnects 31c, 31e, and 31f, respectively. Faces of the nanosheets 21a, 21b, 21d, 21e, and 21h on the second side as the other side in the X direction are exposed from gate interconnects 31a to 31d and 31g, respectively.

10. 发明授权

US11450688B2 Semiconductor integrated circuit device 有权
公开(公告)号：US11450688B2
公开(公告)日：2022-09-20
申请号：US17104563
申请日：2020-11-25
申请人： SOCIONEXT INC.
发明人： Hiroyuki Shimbo
IPC分类号： H01L27/00 , H01L27/118 , H01L29/06 , H01L27/092 , H01L27/02 , H01L21/8238
摘要： Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

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