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1. 发明申请

US20130061016A1 VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER 审中-公开
标题翻译：嵌入在内存控制器中的多个数据处理器
公开(公告)号：US20130061016A1
公开(公告)日：2013-03-07
申请号：US13605880
申请日：2012-09-06
申请人： Ignazio Antonino Urzi , Nicolas Graciannette
发明人： Ignazio Antonino Urzi , Nicolas Graciannette
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F21/79
摘要： A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed.
摘要翻译：第一引擎和存储器访问控制器各自被配置为并行地接收存储器操作信息。响应于接收到存储器操作信息，第一引擎准备执行与存储器操作相关联的存储器数据的功能，并且存储器控制器被配置为准备存储器以使得执行存储器操作。

2. 发明申请

US20120210288A1 METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING FOR SOURCE IDENTIFIER ALLOCATION 有权
标题翻译：用于将多个DIES接口与用于源标识符分配的映射的方法和装置
公开(公告)号：US20120210288A1
公开(公告)日：2012-08-16
申请号：US13028250
申请日：2011-02-16
申请人： Ignazio Antonino URZI , Philippe D'AUDIGIER , Olivier SAUVAGE , Stuart RYAN , Andrew Michael JONES
发明人： Ignazio Antonino URZI , Philippe D'AUDIGIER , Olivier SAUVAGE , Stuart RYAN , Andrew Michael JONES
IPC分类号： G06F17/50
CPC分类号： G09G5/006 , G06F3/14 , Y02T10/82
摘要： A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.
摘要翻译：包装包括模具和至少一个另外的模具。管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。管芯还具有映射电路，其被配置为向接收到的事务分配本地源身份信息作为源身份信息，本地源身份信息包括一组可重用的本地源身份信息。这样可确保以相同原始来源身份和目标标记的事务的顺序，并允许使用不同的源标识符标记的事务处理不正常。

3. 发明申请

US20220239059A1 APPARATUS FOR COMPENSATING PARASITIC IMPEDANCE FOR INTEGRATED CIRCUITS 有权
公开(公告)号：US20220239059A1
公开(公告)日：2022-07-28
申请号：US17720139
申请日：2022-04-13
申请人： STMICROELECTRONICS (RESEARCH & DEVELOPMENT ) LIMITED , STMICROELECTRONICS (GRENOBLE2) SAS
发明人： Denise Tingxi LEE , Neale DUTTON , Nicolas MOENECLAEY , Jerome ANDRIOT-BALLET
IPC分类号： H01S5/026 , H01S5/042 , H01S5/183
摘要： A laser diode driver circuit includes a first pair of contacts and connectors coupled to an anode of the laser diode. An inductance of each of the first pair of contacts and connectors is the same. A second pair of contacts and connectors are coupled to a cathode of the laser diode. An inductance of each of the second pair of contacts and connectors is the same. The laser diode driver circuit also includes current driving circuitry.

4. 发明申请

US20130070830A1 CHARACTERIZATION OF THE JITTER OF A CLOCK SIGNAL 审中-公开
标题翻译：时钟信号抖动的表征
公开(公告)号：US20130070830A1
公开(公告)日：2013-03-21
申请号：US13613200
申请日：2012-09-13
申请人： Herve LE-GALL
发明人： Herve LE-GALL
IPC分类号： H04B17/00
CPC分类号： G01R31/31709
摘要： A method for characterizing jitter of an internal clock signal of a circuit may include generating a series of samples of the internal clock signal by a reference clock signal, comparing the word formed by the N most recent samples of the series to an N-bit pattern, where N is an integer greater than, or equal to 2, and incrementing a first counter if the word complies with the pattern. The method may also include incrementing a second counter when the count of the first counter reaches a first threshold X1, and incrementing a third counter when the count of the first counter reaches a second threshold different from the first. The method may include calculating an average p and a standard deviation σ of a Gaussian density curve as a function of the counts reached in the second and third counters.
摘要翻译：用于表征电路的内部时钟信号的抖动的方法可以包括通过参考时钟信号产生内部时钟信号的一系列样本，将由N个最近的序列样本形成的字与N位模式进行比较，其中N是大于或等于2的整数，并且如果该字符合该图案则递增第一计数器。该方法还可以包括当第一计数器的计数达到第一阈值X1时增加第二计数器，并且当第一计数器的计数达到与第一计数器不同的第二阈值时递增第三计数器。该方法可以包括计算平均值p和标准差＆sgr; 作为第二和第三计数器中达到的计数的函数的高斯密度曲线。

5. 发明申请

US20120210093A1 METHOD AND APPARATUS FOR INTERFACING MULTIPLE DIES WITH MAPPING TO MODIFY SOURCE IDENTITY 有权
标题翻译：用于与多个摄像头进行接口以修改源标识的方法和装置
公开(公告)号：US20120210093A1
公开(公告)日：2012-08-16
申请号：US13028383
申请日：2011-02-16
申请人： Ignazio Antonino URZI , Philippe D'AUDIGIER , Olivier SAUVAGE , Stuart RYAN , Andrew Michael JONES
发明人： Ignazio Antonino URZI , Philippe D'AUDIGIER , Olivier SAUVAGE , Stuart RYAN , Andrew Michael JONES
IPC分类号： G06F12/02
CPC分类号： G06F13/385 , A01C7/04 , A01C7/20 , G06F15/173 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/12041 , H01L2924/15311 , H01L2924/00 , H01L2924/014
摘要： A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.
摘要翻译：包装包括模具和至少一个另外的模具。管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。芯片还具有映射电路，其被配置为接收包括至少第一源标识信息的事务请求，其中第一源标识信息与另外裸片上的事务请求的源相关联。映射电路被配置为修改事务请求以用本地源标识信息替换第一源标识信息，其中本地源标识信息与映射电路相关联。映射电路被配置为修改所接收的事务请求以在另外的字段中提供所述第一源标识信息。

6. 发明授权

US10750188B2 Method and device for dynamically monitoring the encoding of a digital multidimensional signal 有权
公开(公告)号：US10750188B2
公开(公告)日：2020-08-18
申请号：US16412106
申请日：2019-05-14
申请人： STMicroelectronics (Grenoble 2) SAS
发明人： Mariano Bona , Fritz Lebowsky
IPC分类号： H04N19/154 , H04N19/132 , H04N19/196 , H04N19/176 , H04N19/895 , H04N19/182 , H04N19/15 , H04N19/103 , H04N19/593
摘要： A method is provided for encoding a digital signal as an encoded signal. The method includes performing a plurality of localized encodings of a digital signal to generate a set of encoded local signals. Localized encodings are performed for a first sample of the digital signal. A plurality of physical quantities is assigned to the first sample. The set of encoded local signals includes an encoded local signal associated with each physical quantity of the plurality of physical quantities. The method further includes analyzing a characteristic associated with an encoded signal to determine a measured value of the characteristic. The encoded signal includes the set of encoded local signals. The method also includes adjusting a first encoding parameter associated with the plurality of localized encodings according to the measured value of the characteristic and a target value of the characteristic. The first encoding parameter is adjusted for a second sample of the digital signal. The second sample is processed after the first sample.

7. 发明授权

US10530563B2 Clock synchronization device 有权
公开(公告)号：US10530563B2
公开(公告)日：2020-01-07
申请号：US15898816
申请日：2018-02-19
申请人： STMicroelectronics (Grenoble 2) SAS
发明人： Etienne Cesar
IPC分类号： H04L7/033 , H03L7/085 , H03L7/099
摘要： In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.

8. 发明授权

US09313464B2 Checking device and method based on image processing 有权
标题翻译：基于图像处理检查设备和方法
公开(公告)号：US09313464B2
公开(公告)日：2016-04-12
申请号：US13808954
申请日：2011-07-11
申请人： Florent Pellerin , Jacques Dumarest
发明人： Florent Pellerin , Jacques Dumarest
IPC分类号： H04N7/12 , H04N5/228 , A61J7/00 , G06F17/00 , G03B21/00 , B65D83/04 , H04N7/18 , G06F19/00 , G07F9/02 , G07F17/00 , G07G1/00 , A61J7/04
CPC分类号： H04N7/183 , A61J7/04 , G06F19/00 , G06F19/3462 , G07F9/026 , G07F17/0092 , G07G1/0036
摘要： A device for detecting objects includes a vessel intended to contain the objects. A sensor is configured to capture at least one image of the vessel. A processing device is configured to process at least one captured image by detecting objects of the at least one captured image, extracting characteristics of each detected object, and generating a list of the characteristics of each detected object. A memory stores the generated list, the memory also configured to store a first reference list of object characteristics. The processing device further generates a second list of characteristics from a captured image. The characteristics of each object of the second list are compared with, respectively, the characteristics of each object of the reference list.
摘要翻译：用于检测物体的装置包括用于容纳物体的容器。传感器被配置为捕获容器的至少一个图像。处理装置被配置为通过检测所述至少一个拍摄图像的对象，提取每个检测到的对象的特征以及生成每个检测到的对象的特征的列表来处理至少一个拍摄图像。存储器存储生成的列表，存储器还被配置为存储对象特征的第一参考列表。处理装置还从捕获的图像生成第二特征列表。将第二列表的每个对象的特征分别与参考列表的每个对象的特征进行比较。

9. 发明申请

US20100232687A1 METHOD AND DEVICE FOR REORDERING IMAGE DATA HAVING A DISTRIBUTION OF THE BAYER PATTERN TYPE 有权
标题翻译：用于重新分析贝叶片类型的图像数据的方法和装置
公开(公告)号：US20100232687A1
公开(公告)日：2010-09-16
申请号：US12723930
申请日：2010-03-15
申请人： Ludovic Chotard
发明人： Ludovic Chotard
IPC分类号： G06K9/03
CPC分类号： H04N9/045
摘要： The present disclosure relates to a method for reordering data organized according to a matrix configuration, comprising steps of reading line by line input data having a matrix configuration (3) to obtain an input data flow, and of processing a line of the input data involving: transferring into an output data flow a datum of the input data flow, belonging to the processed line, and transferring into the output data flow at least one datum of the input data flow stored beforehand, belonging to a previous line and having a same rank in the matrix configuration as the datum transferred from the processed line, and storing a datum of the input data flow belonging to the processed line and not transferred into the output data flow, to replace the transferred datum, belonging to a previous line.
摘要翻译：本公开涉及一种用于对根据矩阵配置组织的数据进行重新排序的方法，包括以下步骤：读取具有矩阵配置（3）的逐行输入数据以获得输入数据流，以及处理涉及：将属于处理线的输入数据流的数据传输到输出数据流中，并将预先存储的属于前一行并具有相同等级的输入数据流的至少一个数据传送到输出数据流中在作为从处理线路传送的基准的矩阵结构中，存储属于处理线路的输入数据流的基准而不被传送到输出数据流中，以替换属于前一行的传送数据。

10. 发明授权

US10832780B2 Method for programming a non-volatile memory device and corresponding non-volatile memory device 有权
公开(公告)号：US10832780B2
公开(公告)日：2020-11-10
申请号：US16432369
申请日：2019-06-05
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Alps) SAS
发明人： Leonardo Valencia Rissetto , Elise Le Roux , Christophe Forel
IPC分类号： G11C16/06 , G11C16/10 , G11C16/04
摘要： A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.

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