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1. 发明授权

US11374120B2 Apparatus, system and method of an electrostatically formed nanowire (EFN) 有权
公开(公告)号：US11374120B2
公开(公告)日：2022-06-28
申请号：US16870980
申请日：2020-05-10
申请人： TOWER SEMICONDUCTOR LTD. , RAMOT at Tel Aviv University Ltd.
发明人： Zohar Shaked , Yakov Roizin , Menachem Vofsy , Alexey Heiman , Yossi Rosenwaks , Klimentiy Shimanovich , Yhonatan Vaknin
IPC分类号： H01L29/775 , G01N27/414 , H01L29/10 , H01L27/12 , H01L29/66 , H01L29/423
摘要： For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

2. 发明申请

US20220026266A1 ULTRAVIOLET RADIATION SENSOR 有权
公开(公告)号：US20220026266A1
公开(公告)日：2022-01-27
申请号：US17444560
申请日：2021-08-05
申请人： Tower Semiconductor Ltd.
发明人： Pikhay Evgeny , Yakov Roizin , Michael Yampolsky
IPC分类号： G01J1/42 , G01J1/44
摘要： A UV radiation sensor that includes an area that is filled with a dielectric material, the area comprises a first portion of a first thickness and a second trench portion with dielectric of a second thickness, wherein the first thickness is smaller than the second thickness; a floating gate that comprises a first floating gate portion that is positioned above the first area portion and a second floating gate portion that is positioned above the trench portion, wherein the second floating gate portion comprises multiple segments, wherein there are one or more gaps between two or more of the multiple segments; a charging element for charging the floating gate; and a readout element for reading the floating gate.

3. 发明申请

US20210341632A1 HIGH RESOLUTION RADIATION SENSOR BASED ON SINGLE POLYSILICON FLOATING GATE ARRAY 有权
公开(公告)号：US20210341632A1
公开(公告)日：2021-11-04
申请号：US16861652
申请日：2020-04-29
申请人： Tower Semiconductor Ltd.
发明人： Yakov Roizin , Evgeny Pikhay , Vladislav Dayan
IPC分类号： G01T1/02 , H01L27/146
摘要： A method for radiation dosage measurement includes: (1) exposing a plurality of single-poly floating gate sensor cells to radiation; (2) measuring threshold voltage differences between logical pairs of the exposed sensor cells using differential read operations, wherein the sensor cells of each logical pair are separated by a distance large enough that radiation impinging on one of the sensor cells does not influence the other sensor cell; (3) determining whether each logical pair of exposed sensor cells is influenced by exposure to the radiation in response to the corresponding measured threshold voltage difference; and (4) determining a dosage of the radiation in response to the number of logical pairs of the exposed sensor cells determined to be influenced by exposure to the radiation. A non-radiation influenced threshold voltage shift may be measured and used in determining whether each logical pair of exposed sensor cells is influenced by radiation exposure.

4. 发明申请

US20210242326A1 Method Of Forming A GaN Sensor Having A Controlled And Stable Threshold Voltage 有权
公开(公告)号：US20210242326A1
公开(公告)日：2021-08-05
申请号：US16781272
申请日：2020-02-04
申请人： Tower Semiconductor Ltd.
发明人： Ruth Shima-Edelstein , Ronen Shaul , Roy Strul , Anatoly Sergienko , Liz Poliak , Ido Gilad , Alex Sirkis , Yakov Roizin
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/20 , H01L29/205
摘要： A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.

5. 发明授权

US10707120B1 SOI devices with air gaps and stressing layers 有权
公开(公告)号：US10707120B1
公开(公告)日：2020-07-07
申请号：US16373925
申请日：2019-04-03
申请人： Tower Semiconductor Ltd.
发明人： Bouhnik Yami , Nagar Magi , Barhum Liat , Alexey Heiman , Yakov Roizin
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/762 , H01L29/06 , H01L27/12
摘要： An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.

6. 发明授权

US10522388B1 Method of forming high-voltage silicon-on-insulator device with diode connection to handle layer 有权
公开(公告)号：US10522388B1
公开(公告)日：2019-12-31
申请号：US16112466
申请日：2018-08-24
申请人： Tower Semiconductor Ltd.
发明人： Einat Ophir Arad , Sharon Levin , Allon Parag , Eran Lipp , Yosef Avrahamov
IPC分类号： H01L21/74 , H01L27/12 , H01L21/84 , H01L29/78 , H01L29/861 , H01L29/06
摘要： An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.

7. 发明申请

US20180005820A1 COMPOSITION AND METHOD FOR FORMING A DIELECTRIC LAYER 审中-公开
公开(公告)号：US20180005820A1
公开(公告)日：2018-01-04
申请号：US15690392
申请日：2017-08-30
申请人： Ramot at Tel-Aviv University Ltd. , Tower Semiconductor Ltd.
发明人： Simon LITSYN , Gil ROSENMAN , Amir HANDELMAN , Yakov ROIZIN
IPC分类号： H01L21/02 , C08J9/26 , B82Y40/00 , B82Y30/00
CPC分类号： H01L21/02203 , B82Y30/00 , B82Y40/00 , C08J9/26 , C08J2201/042 , C08J2205/024 , C08J2383/04 , H01L21/02164 , H01L21/02211 , H01L21/02255 , H01L21/02282
摘要： A porous layer is described. The porous layer comprises a solidified sol-gel inorganic material having a distribution of nanometric voids, wherein at least some of nanometric voids are at least partially coated internally by carbon or a hydrophobic substance containing carbon.

8. 发明授权

US09806174B2 Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure 有权
公开(公告)号：US09806174B2
公开(公告)日：2017-10-31
申请号：US15254836
申请日：2016-09-01
申请人： Tower Semiconductor Ltd.
发明人： Sagy Levy , Sharon Levin , Noel Berkovitch
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L21/265 , H01L21/266 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/78 , H01L21/32 , H01L21/02 , H01L21/225 , H01L21/3105 , H01L27/06 , H01L21/324 , H01L29/08 , H01L29/40
CPC分类号： H01L29/66681 , H01L21/02233 , H01L21/02255 , H01L21/2253 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L21/31053 , H01L21/32 , H01L21/324 , H01L21/76224 , H01L21/823418 , H01L21/823462 , H01L21/823814 , H01L21/823857 , H01L27/0617 , H01L27/0922 , H01L29/0634 , H01L29/0653 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.

9. 发明授权

US09728632B2 Deep silicon via as a drain sinker in integrated vertical DMOS transistor 有权
公开(公告)号：US09728632B2
公开(公告)日：2017-08-08
申请号：US14556196
申请日：2014-11-30
申请人： Tower Semiconductor Ltd.
发明人： Sharon Levin , Zachary K. Lee , Shye Shapira
IPC分类号： H01L29/66 , H01L29/78 , H01L27/088 , H01L21/8234 , H01L27/092 , H01L29/417 , H01L29/49 , H01L21/8238
CPC分类号： H01L29/7809 , H01L21/823487 , H01L21/82385 , H01L21/823857 , H01L21/823885 , H01L27/088 , H01L27/0922 , H01L29/41741 , H01L29/4916
摘要： A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDSON) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSI processes, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.

10. 发明授权

US09640607B2 Die including a high voltage capacitor 有权
公开(公告)号：US09640607B2
公开(公告)日：2017-05-02
申请号：US14637432
申请日：2015-03-04
申请人： Tower Semiconductor Ltd.
发明人： Sharon Levin
IPC分类号： H01L27/01 , H01L49/02 , G06F17/50 , H01L27/06 , H01L23/522
CPC分类号： H01L28/75 , G06F17/5081 , G06F2217/06 , G06F2217/78 , H01L23/5223 , H01L27/0635
摘要： According to an embodiment of the invention there may be provided a die that may include a first capacitor layer that comprises (a) a first capacitor conductive plate, and (b) a first capacitor layer dielectric material that partially surrounds the first capacitor conductive plate; a first conductor; an intermediate metal layer that comprises (a) an intermediate metal layer conductor that is made of Copper, and (b) an intermediate metal layer dielectric material that partially surrounds the intermediate metal layer conductor; wherein the first conductor is positioned between a substrate of the die and the intermediate metal layer; a redistribution layer that comprises (a) a redistribution layer conductor that is electrically coupled to an interface pad of the die, (b) a second capacitor conductive plate, and (c) a redistribution layer dielectric material that partially surrounds the redistribution layer conductor and the second capacitor conductive plate; wherein a certain portion of the intermediate metal layer dielectric material is positioned between the first and second capacitor conductive plates; wherein at least the certain portion of the intermediate metal layer dielectric material, the first capacitor conductive plate and the second capacitor conductive plate form a high voltage capacitor; and wherein the intermediate metal layer conductor is configured to supply power to a group of transistors of the die while the first conductor is configured to supply power only to a sub-group of the transistors of the die.

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