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1. 发明授权

US11347650B2 Word type/boundary propagation with memory performance applications 有权
公开(公告)号：US11347650B2
公开(公告)日：2022-05-31
申请号：US15891322
申请日：2018-02-07
申请人： Advanced Micro Devices, Inc.
发明人： David A. Roberts , Elliot H. Mednick
IPC分类号： G06F12/0895 , G06F3/06 , G06F12/06
摘要： A method includes, for each data value in a set of one or more data values, determining a boundary between a high order portion of the data value and a low order portion of the data value, storing the low order portion at a first memory location utilizing a low data fidelity storage scheme, and storing the high order portion at a second memory location utilizing a high data fidelity storage scheme for recording data at a higher data fidelity than the low data fidelity storage scheme.

2. 发明授权

US11243884B2 Control flow guided lock address prefetch and filtering 有权
公开(公告)号：US11243884B2
公开(公告)日：2022-02-08
申请号：US16190111
申请日：2018-11-13
申请人： Advanced Micro Devices, Inc.
发明人： Susumu Mashimo , John Kalamatianos
IPC分类号： G06F12/0862
摘要： A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

3. 发明授权

US11188640B1 Platform firmware isolation 有权
公开(公告)号：US11188640B1
公开(公告)日：2021-11-30
申请号：US16110329
申请日：2018-08-23
申请人： Advanced Micro Devices, Inc.
发明人： Jeremy W Powell , David A Kaplan
IPC分类号： G06F17/00 , H04L29/06 , G06F21/53 , G06F21/74 , G06F21/57 , G06F21/60
摘要： A method includes establishing an isolated execution environment for executing a platform firmware operating mode subroutine in a platform firmware operating mode. In response to receiving an interrupt, the platform firmware operating mode subroutine is executed in the isolated execution environment. In response to detecting an attempted access of a hardware resource resulting from execution of the platform firmware operating mode subroutine, the attempted access is blocked when the attempted access violates a security policy.

4. 发明授权

US10171382B2 Mechanism of identifying available memory resources in a network of multi-level memory modules 有权
公开(公告)号：US10171382B2
公开(公告)日：2019-01-01
申请号：US14748209
申请日：2015-06-23
申请人： Advanced Micro Devices, Inc.
发明人： Sergey Blagodurov
IPC分类号： G06F15/173 , H04L12/911 , G06F3/06 , H04L12/721
摘要： A method of managing memory in a network of nodes includes identifying memory resources for each of the plurality of nodes connected to the network, storing memory resource information describing the memory resources, and based on the stored memory resource information, allocating a portion of the memory resources for execution of instructions in a workload, where at least a first node of the plurality of nodes is configured to execute the workload using the allocated portion of the memory resources.

5. 发明授权

US10049044B2 Asynchronous cache flushing 有权
公开(公告)号：US10049044B2
公开(公告)日：2018-08-14
申请号：US15181415
申请日：2016-06-14
申请人： Advanced Micro Devices, Inc.
发明人： Michael Boyer , Gabriel Loh , Nuwan Jayasena
IPC分类号： G06F12/0804 , G06F12/0806 , G06F12/0842
摘要： Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

6. 发明授权

US09947386B2 Thermal aware data placement and compute dispatch in a memory system 有权
公开(公告)号：US09947386B2
公开(公告)日：2018-04-17
申请号：US14492045
申请日：2014-09-21
申请人： Advanced Micro Devices, Inc.
发明人： Manish Arora , Indrani Paul , Yasuko Eckert , Nuwan Jayasena , Dong Ping Zhang
IPC分类号： G11C11/4078 , G11C11/4096 , G11C5/02 , G11C7/04 , G11C8/12
CPC分类号： G11C11/4096 , G11C5/025 , G11C7/04 , G11C8/12
摘要： A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

7. 发明授权

US09438414B2 Virtualized SHA computational engine 有权
标题翻译：虚拟化SHA计算引擎
公开(公告)号：US09438414B2
公开(公告)日：2016-09-06
申请号：US14058102
申请日：2013-10-18
申请人： Advanced Micro Devices, Inc.
发明人： Winthrop J Wu
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , H04L2209/12
摘要： A computational engine may comprise a working memory configured to receive a first input message and a second input message, a context memory coupled with the working memory, wherein the context memory is configured to simultaneously store a first context corresponding to the first input message and a second context corresponding to the second input message, and a set of computational elements coupled with the working memory and coupled with the context memory, wherein the set of computational elements is configured to finish generating a first output digest based on the first input message and a first context after starting generation of a second output digest based the second input message and a second context and before finishing the generation of the second output digest.
摘要翻译：计算引擎可以包括被配置为接收第一输入消息和第二输入消息的工作存储器，与工作存储器耦合的上下文存储器，其中上下文存储器被配置为同时存储对应于第一输入消息的第一上下文，以及第二上下文对应于第二输入消息，以及与工作存储器耦合并与上下文存储器耦合的一组计算元件，其中该组计算元件被配置为基于第一输入消息完成生成第一输出摘要，并且基于第二输入消息和第二上下文开始生成第二输出摘要之后，以及在完成第二输出摘要的生成之前的第一上下文。

8. 发明授权

US09086916B2 Architecture for efficient computation of heterogeneous workloads 有权
标题翻译：用于高效计算异构工作负载的体系结构
公开(公告)号：US09086916B2
公开(公告)日：2015-07-21
申请号：US13894990
申请日：2013-05-15
申请人： Advanced Micro Devices, Inc.
发明人： Winthrop J. Wu
IPC分类号： G06T1/20 , G06F9/38 , G06F9/48
CPC分类号： G06F9/4843 , G06F9/3877 , G06F9/4881 , G06F9/5066 , G06F2209/5017 , G06T1/20
摘要： Embodiments of a workload management architecture may include an input configured to receive workload data for a plurality of commands, a DMA block configured to divide the workload data for each command of the plurality of commands into a plurality of job packets, a job packet manager configured to assign one of the plurality of job packets to one of a plurality of fixed function engines (FFEs) coupled with the job packet manager, where each of the plurality of FFEs is configured to receive one or more of the plurality of job packets and generate one or more output packets based on the workload data in the received one or more job packets.
摘要翻译：工作负载管理架构的实施例可以包括被配置为接收多个命令的工作负载数据的输入，被配置为将多个命令的每个命令的工作负载数据划分成多个作业分组的DMA块，配置的作业分组管理器将多个作业分组中的一个分配给与作业分组管理器耦合的多个固定功能引擎（FFE）中的一个，其中多个FFE中的每一个被配置为接收多个作业分组中的一个或多个并生成基于所接收的一个或多个作业分组中的工作负载数据的一个或多个输出分组。

9. 发明授权

US11507517B2 Scalable region-based directory 有权
公开(公告)号：US11507517B2
公开(公告)日：2022-11-22
申请号：US17033212
申请日：2020-09-25
申请人： Advanced Micro Devices, Inc.
发明人： Amit Apte , Ganesh Balakrishnan
IPC分类号： G06F12/0895
摘要： Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.

10. 发明授权

US11455153B2 Dynamic instances semantics 有权
公开(公告)号：US11455153B2
公开(公告)日：2022-09-27
申请号：US16544796
申请日：2019-08-19
申请人： Advanced Micro Devices, Inc.
发明人： Nicolai Haehnle
IPC分类号： G06F8/41
摘要： A computing system includes a processor and a memory storing instructions for a compiler that, when executed by the processor, cause the processor to generate a control flow graph of program source code by receiving the program source code in the compiler, in the compiler, generating a structure point representation based on the received program source code by inserting into the program source code a set of structure points including an anchor structure point and a join structure point associated with the anchor structure point, and based on the structure point representation, generating the control flow graph including a plurality of blocks each representing a portion of the program source code. In the control flow graph, a block A between the anchor structure point and the join structure point post-dominates each of the one or more divergent branches between the anchor structure point and the join structure point.

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