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1. 发明授权

US08099098B2 Methods and apparatus for planning wireless data networks using analytical modeling of user level performance 有权
标题翻译：使用用户级别性能分析建模来规划无线数据网络的方法和装置
公开(公告)号：US08099098B2
公开(公告)日：2012-01-17
申请号：US10422286
申请日：2003-04-24
申请人： Simon C. Borst , Krishnan Kumaran , Kavita Ramanan , Philip A. Whiting
发明人： Simon C. Borst , Krishnan Kumaran , Kavita Ramanan , Philip A. Whiting
IPC分类号： H04W40/00
CPC分类号： H04W16/18 , H04W24/00 , H04W28/18
摘要： Techniques and systems for planning of wireless networks are described. A system according to an aspect of the present invention receives inputs describing traffic statistics for a wireless network and computes network specifications. The system uses the traffic statistics and network specifications as inputs to a computationally tractable model used to compute parameters for the user level performance of the wireless network. The model may suitably be a processor sharing queuing model. The model employed by the planning system allows analytical solution for the desired user level parameters, given the characteristics and conditions entered as inputs and the intended network layout characteristics. Once a set of user level performance parameters has been computed, the values of the parameters are examined to determine if they meet predetermined requirements, in an iterative process continuing until a set of specifications has been developed that produces parameters meeting the requirements.
摘要翻译：描述了无线网络规划的技术和系统。根据本发明的一个方面的系统接收描述无线网络的流量统计的输入并计算网络规范。该系统使用流量统计和网络规范作为用于计算用于无线网络的用户级性能的参数的计算容易模型的输入。该模型可以适当地是处理器共享排队模型。考虑到作为输入输入的特性和条件以及预期的网络布局特性，计划系统采用的模型允许针对所需用户级别参数的分析解决方案。一旦已经计算出一组用户级性能参数，则检查参数的值以确定它们是否满足预定的要求，在迭代过程中持续直到已经开发出一组规范来产生满足要求的参数。

2. 发明授权

US08073272B2 Methods and apparatus for video decoding 有权
标题翻译：视频解码方法和装置
公开(公告)号：US08073272B2
公开(公告)日：2011-12-06
申请号：US12792228
申请日：2010-06-02
申请人： Doina Petrescu , Trampas Stern , Marco Jacobs , Dan Searles , Charles W. Kurak, Jr.
发明人： Doina Petrescu , Trampas Stern , Marco Jacobs , Dan Searles , Charles W. Kurak, Jr.
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N19/42 , H04N19/436 , H04N19/44 , H04N19/61
摘要： Techniques for performing the processing of blocks of video in multiple stages. Each stage is executed for blocks of data in the frame that need to go through that stage, based on the coding type, before moving to the next stage. This order of execution allows blocks of data to be processed in a nonsequential order, unless the blocks need to go through the same processing stages. Multiple processing elements (PEs) operating in SIMD mode executing the same task and operating on different blocks of data may be utilized, avoiding idle times for the PEs. In another aspect, inverse scan and dequantization operations for blocks of data are merged in a single procedure operating on multiple PEs operating in SIMD mode. This procedure makes efficient use of the multiple PEs and speeds up processing by combining two operations, inverse scan (reordering) and dequantization, which load the execution units differently. The reordering loads mainly the load and store units of the PEs, while the dequantization loads mainly other units. By combining the inverse scan and dequantization in an efficient VLIW packing performance, processing gain is achieved.
摘要翻译：用于在多个阶段中执行视频块处理的技术。在移动到下一阶段之前，根据编码类型，在需要经过该阶段的帧中的数据块执行每个阶段。这种执行顺序允许以非顺序的顺序处理数据块，除非块需要经历相同的处理阶段。可以利用以SIMD模式运行的执行相同任务并在不同的数据块上操作的多个处理元件（PE），避免了PE的空闲时间。在另一方面，用于数据块的逆扫描和去量化操作在以在SIMD模式下操作的多个PE上操作的单个过程中合并。该过程有效地利用多个PE，并通过组合两个操作，反向扫描（重新排序）和去量化来加快处理，从而不同地加载执行单元。重新排序负载主要是PE的负载和存储单元，而反量化主要负载其他单元。通过在有效的VLIW包装性能中组合逆扫描和去量化，实现了处理增益。

3. 发明授权

US07941648B2 Methods and apparatus for dynamic instruction controlled reconfigurable register file 有权
公开(公告)号：US07941648B2
公开(公告)日：2011-05-10
申请号：US12132001
申请日：2008-06-03
申请人： Gerald George Pechanek , Edward A. Wolff
发明人： Gerald George Pechanek , Edward A. Wolff
IPC分类号： G06F7/38
CPC分类号： G06F9/30112 , G06F9/30014 , G06F9/30036 , G06F9/30134 , G06F9/30145 , G06F9/30192 , G06F9/34 , G06F9/3851 , G06F9/3853 , G06F9/3885
摘要： A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.

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