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1. 发明申请

US20140223141A1 SHARING TLB MAPPINGS BETWEEN CONTEXTS 有权
标题翻译：共享对象之间的TLB映射
公开(公告)号：US20140223141A1
公开(公告)日：2014-08-07
申请号：US13997789
申请日：2011-12-29
申请人： Jonathan D. Combs , Jason W. Brandt , Benjamin C. Chaffin , Julio Gago , Andrew F. Glew
发明人： Jonathan D. Combs , Jason W. Brandt , Benjamin C. Chaffin , Julio Gago , Andrew F. Glew
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3851 , G06F12/0842 , G06F12/1036 , G06F2212/1024 , G06F2212/657
摘要： In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.
摘要翻译：在一些实现中，处理器可以包括诸如翻译后备缓冲器的数据结构，其包括包含具有虚拟地址的第一映射信息和与第一线程相关联的第一上下文的条目。控制逻辑可以接收对具有虚拟地址的第二映射信息和与第二线程相关联的第二上下文的请求。控制逻辑可以确定与第二上下文相关联的第二映射信息是否等于数据结构条目中的第一映射信息。如果第二映射信息等同于第一映射信息，则控制逻辑可以将第二线程与数据结构条目中包含的第一映射信息相关联，以共享第一线程和第二线程之间的条目。

2. 发明申请

US20130036464A1 Processor operable to ensure code integrity 有权
标题翻译：处理器可操作以确保代码完整性
公开(公告)号：US20130036464A1
公开(公告)日：2013-02-07
申请号：US13136670
申请日：2011-08-04
申请人： Andrew F. Glew , Daniel A. Gerrity , Clarence T. Tegreene
发明人： Andrew F. Glew , Daniel A. Gerrity , Clarence T. Tegreene
IPC分类号： G06F21/00
CPC分类号： G06F21/52 , G06F9/32 , G06F9/322 , G06F21/50 , G06F21/71
摘要： A processor can be used to ensure that program code can only be used for a designed purpose and not exploited by malware. Embodiments of an illustrative processor can comprise logic operable to execute a program instruction and to distinguish whether the program instruction is a legitimate branch instruction or a non-legitimate branch instruction.
摘要翻译：处理器可用于确保程序代码只能用于设计目的而不被恶意软件利用。说明性处理器的实施例可以包括可操作以执行程序指令并区分程序指令是否为合法分支指令还是非合法分支指令的逻辑。

3. 发明申请

US20110078389A1 MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS 有权
标题翻译：使用注册扩展管理和实施中央处理单元中的元数据
公开(公告)号：US20110078389A1
公开(公告)日：2011-03-31
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
IPC分类号： G06F9/30 , G06F12/02 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译：一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

4. 发明申请

US20100250792A1 OPPORTUNISTIC IMPROVEMENT OF MMIO REQUEST HANDLING BASED ON TARGET REPORTING OF SPACE REQUIREMENTS 有权
标题翻译：基于目标报告空间要求的MMIO请求处理的机会改进
公开(公告)号：US20100250792A1
公开(公告)日：2010-09-30
申请号：US12415913
申请日：2009-03-31
申请人： David J. Harriman , Andrew F. Glew
发明人： David J. Harriman , Andrew F. Glew
IPC分类号： G06F13/28
CPC分类号： G06F13/16 , G06F9/46 , G06F12/02 , G06F12/063 , G06F12/1027 , G06F13/14 , G06F15/16 , G06F2212/654
摘要： Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.
摘要翻译：描述了存储映射输入/输出（MMIO）请求处理的机会性改进的方法和装置（例如，基于空间要求的目标报告）。在一个实施例中，处理器中的逻辑可以检测要从输入/输出（I / O）设备发送的消息中的一个或多个位。一个或多个比特可以指示对应于I / O设备的一个或多个属性的存储器映射I / O（MMIO）信息。还公开了其他实施例。

5. 发明授权

US06792523B1 Processor with instructions that operate on different data types stored in the same single logical register file 失效
标题翻译：处理器具有对存储在同一个逻辑寄存器文件中的不同数据类型进行操作的指令
公开(公告)号：US06792523B1
公开(公告)日：2004-09-14
申请号：US09363116
申请日：1999-07-27
申请人： Andrew F. Glew , Larry M. Menneneier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Menneneier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
IPC分类号： G06F1200
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/462
摘要： A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears to software as a single logical register file. The first set of instructions appears to access the single logical register file as a flat register file. In addition, a first instruction of a second instruction type operates on the logical register file. However, the first instruction appears to access the logical register file as a stack referenced register file. Furthermore, sometime between starting the execution of the first set of instructions and completing the execution of the first instruction, all tags in a set of tags indicating whether corresponding registers in the single logical register file are empty or non-empty are caused to indicate non-empty states.
摘要翻译：具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。根据本发明的一个方面，第一指令类型的第一组指令对至少逻辑上显示为软件的内容进行操作，作为单个逻辑寄存器文件。第一组指令似乎以平坦寄存器文件的形式访问单个逻辑寄存器文件。此外，第二指令类型的第一指令对逻辑寄存器文件进行操作。但是，第一条指令似乎以堆栈引用的寄存器文件的形式访问逻辑寄存器文件。此外，在开始第一组指令的执行和完成第一指令的执行之间的某个时刻，引起一组标签中指示单个逻辑寄存器文件中的相应寄存器是空还是非空的所有标签，空状态。

6. 发明授权

US06678816B2 Method for optimized representation of page table entries 有权
标题翻译：用于优化页表项表示的方法
公开(公告)号：US06678816B2
公开(公告)日：2004-01-13
申请号：US10441397
申请日：2003-05-19
申请人： Ronny Ronen , Andrew F. Glew , Maury J. Bach , Robert Valentine , Richard A. Uhlig , Opher D. Kahn
发明人： Ronny Ronen , Andrew F. Glew , Maury J. Bach , Robert Valentine , Richard A. Uhlig , Opher D. Kahn
IPC分类号： G06F1204
CPC分类号： G06F12/1009 , G06F2212/652
摘要： Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.
摘要翻译：根据所选择的页面大小和所选择的页面地址来生成预定长度的页面存储器指针记录的方法，所述方法包括以下过程：根据所选择的页面确定页面存储器指针记录中的分隔符位置的动态位置大小和初始页面大小，初始页面大小相应于给定存储器系统中的最小页面大小，将预定值写入动态位置，将与预定值相反的一系列值写入到所选择的页面大小位页面存储器指针记录，当所选择的页面大小不同于初始页面大小时，以及将所选择的页面地址写入页面存储器指针记录的所选页面地址位。

7. 发明授权

US6035393A Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution 失效
标题翻译：失速预测到存储器位置，使用虚拟停止指令识别为不可缓存，直到分支推测分辨率为止
公开(公告)号：US6035393A
公开(公告)日：2000-03-07
申请号：US74561
申请日：1998-05-07
申请人： Andrew F. Glew , Ashwani Gupta
发明人： Andrew F. Glew , Ashwani Gupta
IPC分类号： G06F9/38 , G06F12/02 , G06F9/32
CPC分类号： G06F9/3802 , G06F12/0292 , G06F9/3861 , G06F2212/206
摘要： A computer system includes an instruction prefetching mechanism that detects whether an instruction to be prefetched is located in a region of memory that is uncacheable. To perform an instruction prefetch, an instruction fetch unit (IFU) receives an instruction pointer indicating a memory location containing an instruction to be prefetched. The instruction pointer may be provided by a branch target buffer (BTB) as a result of a branch prediction, or by auxiliary branch prediction mechanisms, or actual execution. The IFU accesses an instruction translation look-aside buffer (ITLB) to determine both the physical address corresponding to the linear address of the instruction pointer and to determine an associated memory type stored therein. If the memory type indicates an uncacheable memory location, the IFU waits until all previous executed instructions have completed. The IFU does this by inserting a "permission-to-fetch" instruction, and then stalling. The IFU remains stalled until either the permission-to-fetch instruction retires or until a branch misprediction is detected. Once a branch misprediction is detected, the permission-to-fetch instruction and all other instructions issued subsequent to the mispredicted branch are squashed. If no previous branch mispredictions are detected, the permission-to-fetch instruction eventually retires, the instruction pointer is reset based on the correct branch, and prefetching continues.
摘要翻译：一种计算机系统包括一个指令预取机构，它检测一个要被预取的指令是否位于不可缓存的存储器区域中。为了执行指令预取，指令提取单元（IFU）接收指示指示包含要被预取的指令的存储器位置的指令指针。指令指针可以由分支预测结果的分支目标缓冲器（BTB）或辅助分支预测机制或实际执行来提供。 IFU访问指令转换后备缓冲器（ITLB）以确定对应于指令指针的线性地址的物理地址并确定存储在其中的相关联的存储器类型。如果存储器类型指示不可缓存的存储器位置，则IFU等待直到所有先前执行的指令已经完成。 IFU通过插入“获取权限”指令，然后停止。 IFU仍然停滞不前，直到获取授权指令退出或直到检测到分支错误预测为止。一旦检测到分支错误预测，则获取权限指令以及在错误预测的分支之后发出的所有其他指令被压缩。如果没有检测到先前的分支错误预测，则获取权限指令最终退出，指令指针基于正确的分支重置，并且继续预取。

8. 发明授权

US5978737A Method and apparatus for hazard detection and distraction avoidance for a vehicle 失效
标题翻译：用于车辆危害检测和分心避免的方法和装置
公开(公告)号：US5978737A
公开(公告)日：1999-11-02
申请号：US953863
申请日：1997-10-16
申请人： Stephen S. Pawlowski , Andrew F. Glew , George R. Hayek , Harshvardhan P. Sharangpani , Richard C. Calderwood
发明人： Stephen S. Pawlowski , Andrew F. Glew , George R. Hayek , Harshvardhan P. Sharangpani , Richard C. Calderwood
IPC分类号： G01S13/93 , G01S7/78
CPC分类号： G01S13/931 , G01S2013/9325 , G01S2013/9342 , G01S2013/9346 , G01S2013/9353 , G01S2013/9357 , G01S2205/002
摘要： A system for detecting hazardous conditions during operation of a vehicle. In one embodiment, the system includes a plurality of sensors that monitor a plurality of conditions and transmit condition signals each representing a measure of a condition. A plurality of rate determination circuits is coupled to the sensors and continually receives the condition signals, wherein each rate determination circuit calculates rates of change for the condition, including a baseline rate of change, and outputs a potential hazard value representing a deviation of a rate of change from the baseline rate that exceeds a predetermined threshold value. An evaluation circuit receives the potential hazard value, calculates a new potential hazard value using the potential hazard value and a rate of change for at least one associated condition and determines whether an actual hazard exists by comparing the new potential hazard value with a stored value that corresponds to the condition.
摘要翻译：一种用于在车辆操作期间检测危险状况的系统。在一个实施例中，系统包括多个监测多个条件的传感器，并且发送各自表示条件测量的条件信号。多个速率确定电路耦合到传感器并且连续地接收条件信号，其中每个速率确定电路计算包括基线变化率的条件的变化率，并且输出表示速率偏差的潜在危险值的基线速率超过预定阈值。评估电路接收潜在危险值，使用潜在危险值和至少一个相关条件的变化率计算新的潜在危险值，并通过将新的潜在危险值与存储值进行比较来确定是否存在实际危害对应于条件。

9. 发明授权

US5751983A Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations 失效
标题翻译：具有处理推测性调度负载操作的内存子系统的乱序处理器
公开(公告)号：US5751983A
公开(公告)日：1998-05-12
申请号：US538594
申请日：1995-10-03
申请人： Jeffrey M. Abramson , David B. Papworth , Haitham H. Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffrey M. Abramson , David B. Papworth , Haitham H. Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/38 , G06F3/38
CPC分类号： G06F9/3834
摘要： A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.
摘要翻译：用于在计算机系统中推测调度和/或执行LOAD的方法和装置包括无序处理器的存储器子系统，其通过将它们分派到存储器子系统中的相应LOAD和STORE缓冲器来处理LOAD和STORE操作。当随后调度LOAD进行执行时，搜索具有未知地址的STORE的存储缓冲区。如果发现任何比发送的LOAD更旧的存储区，并且具有未知地址，则LOAD被标记为未知的存储地址标识（USAID）。当调度STORE执行时，LOAD缓冲区将搜索已被表示为误推测负载的负载。可以防止误导的负载破坏机器的无效数据的架构状态。

10. 发明授权

US5748937A Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions 失效
标题翻译：计算机系统通过在内存访问指令的无序执行期间窥探一个外部总线冲突来维持处理器排序的一致性
公开(公告)号：US5748937A
公开(公告)日：1998-05-05
申请号：US825417
申请日：1997-03-28
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/38
CPC分类号： G06F9/3834
摘要： A computer system having a mechanism for maintaining processor ordering during out-of-order instruction execution is disclosed wherein load memory instructions are accessed according to program order and executed out-of-order in relation to the program order where appropriate. Processors in the system snoop an external bus for bus transactions that conflict with completed load memory instructions before committing results of the completed load memory instructions to an architectural state.
摘要翻译：公开了一种具有用于在无序指令执行期间维持处理器排序的机构的计算机系统，其中根据程序顺序访问加载存储器指令，并且在适当时根据程序顺序执行无序操作。在将完成的加载存储器指令的结果提交到架构状态之前，系统中的处理器会窥探总线事务的外部总线，这些总线事务与完成的加载存储器指令冲突。

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