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1. 发明授权

US08675404B2 Reading method of non-volatile memory device 有权
标题翻译：非易失性存储器件的读取方法
公开(公告)号：US08675404B2
公开(公告)日：2014-03-18
申请号：US13475204
申请日：2012-05-18
申请人： Hyun-Seung Yoo , Sung-Joo Hong , Seiichi Aritome , Seok-Kiu Lee , Sung-Kye Park , Gyu-Seog Cho , Eun-Seok Choi , Han-Soo Joo
发明人： Hyun-Seung Yoo , Sung-Joo Hong , Seiichi Aritome , Seok-Kiu Lee , Sung-Kye Park , Gyu-Seog Cho , Eun-Seok Choi , Han-Soo Joo
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3418
摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.
摘要翻译：一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始，所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替。

2. 发明授权

US06429074B2 Semiconductor memory device and method for fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06429074B2
公开(公告)日：2002-08-06
申请号：US09964420
申请日：2001-09-28
申请人： Jong Wook Lee , Gyu Seog Cho
发明人： Jong Wook Lee , Gyu Seog Cho
IPC分类号： H01L21336
CPC分类号： H01L27/1203 , H01L27/1082
摘要： A method for fabricating a semiconductor memory device using a silicon-on-insulator device, including forming a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.
摘要翻译：一种使用绝缘体上硅器件制造半导体存储器件的方法，包括形成能够减小单元区域与周边区域之间的拓扑结构并防止浮体效应的半导体存储器件。

3. 发明授权

US5693558A Method for fabricating a laser diode 失效
标题翻译：制造激光二极管的方法
公开(公告)号：US5693558A
公开(公告)日：1997-12-02
申请号：US756566
申请日：1996-11-26
申请人： Soo Won Lee , Gyu Seog Cho , Tae Jin Kim , Kyung Seok Oh
发明人： Soo Won Lee , Gyu Seog Cho , Tae Jin Kim , Kyung Seok Oh
IPC分类号： H01S5/00 , H01S5/22 , H01S5/227 , H01L21/20
CPC分类号： H01S5/227 , H01S5/2206 , H01S5/2275
摘要： The present invention relates to a method for fabricating a semiconductor laser diode in optical communication system, having the steps for forming current blocking layers on the resulting structure of the mesa structure and then forming an opening through the current blocking layer on the mesa structure.
摘要翻译：本发明涉及一种在光通信系统中制造半导体激光二极管的方法，具有在台结构的结构上形成电流阻挡层，然后通过台面结构上的电流阻挡层形成开口的步骤。

4. 发明授权

US08658491B2 Manufacturing method of transistor structure having a recessed channel 有权
标题翻译：具有凹陷通道的晶体管结构的制造方法
公开(公告)号：US08658491B2
公开(公告)日：2014-02-25
申请号：US12890926
申请日：2010-09-27
申请人： Gyu Seog Cho
发明人： Gyu Seog Cho
IPC分类号： H01L21/8234
CPC分类号： H01L29/66621 , H01L21/823437 , H01L29/66606 , H01L29/7834
摘要： A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.
摘要翻译：公开了一种半导体器件及其制造方法。所公开的半导体器件包括具有用于限定有源区的器件隔离结构的半导体衬底，有源区是凹陷的，并且沟槽限定在有源区的沟道形成区中; 形成在槽内和上面的门; 栅极隔离物在位于栅极两侧的凹入有源区的部分上形成在栅极的两个侧壁上; 形成在栅极间隔下的有源区中的LDD区; 形成在包括栅极间隔物的栅极两侧的有源区域中的接合区域; 并在接合区域上形成着陆塞。

5. 发明授权

US07825464B2 Semiconductor device with recessed active region and gate in a groove 有权
标题翻译：半导体器件具有凹入的有源区和栅极在沟槽中
公开(公告)号：US07825464B2
公开(公告)日：2010-11-02
申请号：US12020651
申请日：2008-01-28
申请人： Gyu Seog Cho
发明人： Gyu Seog Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/66621 , H01L21/823437 , H01L29/66606 , H01L29/7834
摘要： A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.
摘要翻译：公开了一种半导体器件及其制造方法。所公开的半导体器件包括具有用于限定有源区的器件隔离结构的半导体衬底，有源区是凹陷的，并且沟槽限定在有源区的沟道形成区中; 形成在槽内和上面的门; 栅极隔离物在位于栅极两侧的凹入有源区的部分上形成在栅极的两个侧壁上; 形成在栅极间隔下的有源区中的LDD区; 形成在包括栅极间隔物的栅极两侧的有源区域中的接合区域; 和在连接区域上形成的着陆塞。

6. 发明申请

US20080048252A1 MOSFET DEVICE SUPPRESSING ELECTRICAL COUPLING BETWEEN ADJOINING RECESS GATES AND MTHOD FOR MANUFACTURING THE SAME 失效
标题翻译：用于制造补偿盖的MES的MOS器件抑制电气耦合
公开(公告)号：US20080048252A1
公开(公告)日：2008-02-28
申请号：US11757327
申请日：2007-06-01
申请人： Gyu Seog CHO
发明人： Gyu Seog CHO
IPC分类号： H01L21/336 , H01L29/768
CPC分类号： H01L29/66636 , H01L29/66621
摘要： A MOSFET device comprises a semiconductor substrate having a gate area, a storage node contact area and a bit line contact area. A first groove is defined at a first depth in the gate area and a second groove is defined at a second depth in the bit line contact area. A recess gate is formed in the gate area of the semiconductor substrate including the first groove. A first junction area is formed in the storage node contact area of the semiconductor substrate. A second junction area is formed in the bit line contact area of the semiconductor substrate under the second groove.
摘要翻译： MOSFET器件包括具有栅极区域，存储节点接触区域和位线接触区域的半导体衬底。在栅极区域中的第一深度处限定第一凹槽，并且在位线接触区域中的第二深度处限定第二凹槽。在包括第一凹槽的半导体衬底的栅极区域中形成凹槽。第一接合区域形成在半导体衬底的存储节点接触区域中。第二接合区域形成在半导体衬底的第二沟槽下方的位线接触区域中。

7. 发明申请

US20070090452A1 Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same 审中-公开
标题翻译：用于防止由于栅极层的不对准导致的器件特性劣化的凹陷沟道晶体管及其形成方法
公开(公告)号：US20070090452A1
公开(公告)日：2007-04-26
申请号：US11299544
申请日：2005-12-12
申请人： Gyu Seog Cho , Yong Taik Kim
发明人： Gyu Seog Cho , Yong Taik Kim
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823437 , H01L29/66621
摘要： The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.
摘要翻译：所述凹槽通道晶体管包括：半导体衬底，其包括限定形成有凹部的激活区域的器件绝缘层; 绝缘缓冲图案，其各自形成在基板的表面上的凹部的开口处; 栅极，每个栅极包括形成在凹部中的凹槽和形成在衬底上的顶栅; 间隔件，每个间隔件形成在门的两侧; 以及源极区和漏极区，形成在衬底表面上的每个栅极的两侧，其中由于存在绝缘缓冲图案，源区和漏区具有均匀的掺杂分布。因此，可以防止晶体管的特性由于顶栅与凹槽的不对准而劣化。

8. 发明授权

US06194256B1 Method for fabricating CMOS device 有权
标题翻译：制造CMOS器件的方法
公开(公告)号：US06194256B1
公开(公告)日：2001-02-27
申请号：US09340427
申请日：1999-06-28
申请人： Jong Wook Lee , Gyu Seog Cho
发明人： Jong Wook Lee , Gyu Seog Cho
IPC分类号： H01L21336
CPC分类号： H01L21/84 , H01L27/1203
摘要： Disclosed is a method for fabricating CMOS device using a SOI substrate, and more particularly the method for fabricating CMOS device capable of improving mobility of electron and hole. The present invention provides a method for fabricating CMOS device comprising the steps of: providing an SOI substrate having a stacking structure of a base layer, a buried oxide layer and a semiconductor layer, wherein the SOI substrate is divided into a first region where a PMOS is formed later and a second region where an NMOS is formed later; forming first field oxide films to be contacted with the buried oxide layer by applying a thermal oxidation to a selected portion of the semiconductor layer being disposed in the first region of the SOI substrate; forming trenches with a depth to be contacted with the buried oxide layer in a selected portion of the semiconductor layer being disposed in the second region of the SOI substrate and then forming second field oxide films by filling the trenches with an insulating layer; and forming the PMOS in the portion of the semiconductor layer being defined by those first field oxide films, and the NMOS in the portion of the semiconductor layer being defined by those second field oxide films.
摘要翻译：公开了一种使用SOI衬底制造CMOS器件的方法，更具体地说，涉及一种能够改善电子和空穴的迁移率的CMOS器件的制造方法。本发明提供了一种制造CMOS器件的方法，包括以下步骤：提供具有基底层，掩埋氧化物层和半导体层的堆叠结构的SOI衬底，其中SOI衬底被分成第一区域，其中PMOS 稍后形成NMOS，稍后形成NMOS的第二区域; 通过对设置在所述SOI衬底的所述第一区域中的所述半导体层的选定部分施加热氧化来形成与所述掩埋氧化物层接触的第一场氧化物膜; 在半导体层的选定部分中形成具有与掩埋氧化物层接触的深度的沟槽，其设置在SOI衬底的第二区域中，然后通过用绝缘层填充沟槽来形成第二场氧化膜; 并且在半导体层的由第一场氧化物膜定义的部分中形成PMOS，半导体层的部分中的NMOS由那些第二场氧化物膜限定。

9. 发明申请

US20090159988A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090159988A1
公开(公告)日：2009-06-25
申请号：US12020651
申请日：2008-01-28
申请人： Gyu Seog CHO
发明人： Gyu Seog CHO
IPC分类号： H01L29/00 , H01L21/22
CPC分类号： H01L29/66621 , H01L21/823437 , H01L29/66606 , H01L29/7834
摘要： A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.
摘要翻译：公开了一种半导体器件及其制造方法。所公开的半导体器件包括具有用于限定有源区的器件隔离结构的半导体衬底，有源区是凹陷的，并且沟槽限定在有源区的沟道形成区中; 形成在槽内和上面的门; 栅极隔离物在位于栅极两侧的凹入有源区的部分上形成在栅极的两个侧壁上; 形成在栅极间隔下的有源区中的LDD区; 形成在包括栅极间隔物的栅极两侧的有源区域中的接合区域; 和在连接区域上形成的着陆塞。

10. 发明授权

US07482230B2 Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same 失效
标题翻译：用于防止由于栅极层的不对准导致的器件特性劣化的凹陷沟道晶体管及其形成方法
公开(公告)号：US07482230B2
公开(公告)日：2009-01-27
申请号：US12020686
申请日：2008-01-28
申请人： Gyu Seog Cho , Yong Taik Kim
发明人： Gyu Seog Cho , Yong Taik Kim
IPC分类号： H01L21/335
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823437 , H01L29/66621
摘要： The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.
摘要翻译：所述凹槽通道晶体管包括：半导体衬底，其包括限定形成有凹部的激活区域的器件绝缘层; 绝缘缓冲图案，其各自形成在基板的表面上的凹部的开口处; 栅极，每个栅极包括形成在凹部中的凹槽和形成在衬底上的顶栅; 间隔件，每个间隔件形成在门的两侧; 以及源极区和漏极区，形成在衬底表面上的每个栅极的两侧，其中由于存在绝缘缓冲图案，源区和漏区具有均匀的掺杂分布。因此，可以防止晶体管的特性由于顶栅与凹槽的不对准而劣化。

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