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    • 1. 发明授权
    • Serially interfaced random access memory
    • 串行接口随机存取存储器
    • US08078789B2
    • 2011-12-13
    • US12886186
    • 2010-09-20
    • Joel Henry Hinrichs
    • Joel Henry Hinrichs
    • G06F13/00G06F12/00G11C5/06
    • G06F13/4234
    • A serially interfaced massively parallel Random Access Memory (RAM) includes a matrix of control logic sections on one integrated circuit die, augmented by a switching matrix with an external interface to multiple high speed serial signaling means. A matrix, of the same dimension, of dense memory element arrays is implemented on a different integrated circuit die. One control logic section die and one or more others containing memory sections are joined by appropriate means to form one integrated circuit stack, implementing a matrix of independent memory units. The switching matrix translates command and data content encoded on the external signaling means bidirectionally between internal data and control signals and connects these signals to the control logic sections. Each independent memory unit ably performs atomic read-alter-writes to enable software mutual exclusion operations (MUTEXes). Each and every matrix may guard against defects by having additional rows and/or columns.
    • 串行接口的大容量并行随机存取存储器(RAM)包括一个集成电路管芯上的控制逻辑部分的矩阵,由具有与多个高速串行信令装置的外部接口的交换矩阵增强。 具有相同尺寸的密集存储元件阵列的矩阵在不同的集成电路管芯上实现。 一个控制逻辑部分管芯和一个或多个包含存储器部分的其它部件通过适当的装置连接以形成一个集成电路堆栈,实现独立存储器单元的矩阵。 开关矩阵将在外部信令装置上编码的命令和数据内容在内部数据和控制信号之间双向转换,并将这些信号连接到控制逻辑部分。 每个独立的内存单元都可以执行原子读写操作,以实现软件互斥操作(MUTEXes)。 每个矩阵都可以通过附加的行和/或列来防止缺陷。
    • 8. 发明授权
    • Niobium-tin superconducting coil
    • 铌锡超导线圈
    • US07920040B2
    • 2011-04-05
    • US12711627
    • 2010-02-24
    • Timothy A. AntayaJoel Henry Schultz
    • Timothy A. AntayaJoel Henry Schultz
    • H01F27/30
    • H05H13/00H05H7/04H05H13/02Y10S505/806Y10S505/924Y10T29/49014
    • A Nb3Sn superconducting coil can be formed from a wire including multiple unreacted strands comprising tin in contact with niobium. The strands are wound into a cable, which is then heated to react the tin and niobium to form a cable comprising reacted Nb3Sn strands. The cable comprising the reacted Nb3Sn strands are then mounted in and soldered into an electrically conductive channel to form a reacted cable-in-channel of Nb3Sn strands. The cable-in-channel of reacted Nb3Sn strands are then wound to fabricate a superconducting coil. The Nb3Sn superconducting coil can be used, for example, in a magnet structure for particle acceleration. In one example, the superconducting coil is used in a high-field superconducting synchrocyclotron.
    • Nb3Sn超导线圈可以由包括多个未与反应物接触的锡的未反应的丝线形成。 线束缠绕成电缆,然后将其加热以使锡和铌反应形成包含反应的Nb 3 Sn链的电缆。 然后将包含反应的Nb 3 Sn链的电缆安装在并焊接到导电通道中以形成Nb 3 Sn链的反应的电缆通道。 然后缠绕反应的Nb 3 Sn链的电缆通道以制造超导线圈。 Nb3Sn超导线圈可以用于例如用于粒子加速的磁体结构。 在一个示例中,超导线圈用于高场超导同步回旋加速器。
    • 9. 发明授权
    • Serially interfaced random access memory
    • 串行接口随机存取存储器
    • US07827345B2
    • 2010-11-02
    • US11486897
    • 2006-07-14
    • Joel Henry Hinrichs
    • Joel Henry Hinrichs
    • G06F13/00G06F12/00G11C5/06
    • G06F13/4234
    • A serially interfaced massively parallel Random Access Memory (RAM) includes a matrix of control logic sections on one integrated circuit die, augmented by a switching matrix with an external interface to multiple high speed serial signaling means. A matrix, of the same dimension, of dense memory element arrays is implemented on a different integrated circuit die. One control logic section die and one or more others containing memory sections are joined by appropriate means to form one integrated circuit stack, implementing a matrix of independent memory units. The switching matrix translates command and data content encoded on the external signaling means bidirectionally between internal data and control signals and connects these signals to the control logic sections. Each independent memory unit ably performs atomic read-alter-writes to enable software mutual exclusion operations (MUTEXes). Each and every matrix may guard against defects by having additional rows and/or columns.
    • 串行接口的大容量并行随机存取存储器(RAM)包括一个集成电路管芯上的控制逻辑部分的矩阵,由具有与多个高速串行信令装置的外部接口的交换矩阵增强。 具有相同尺寸的密集存储元件阵列的矩阵在不同的集成电路管芯上实现。 一个控制逻辑部分管芯和一个或多个包含存储器部分的其它部件通过适当的装置连接以形成一个集成电路堆栈,实现独立存储器单元的矩阵。 开关矩阵将在外部信令装置上编码的命令和数据内容在内部数据和控制信号之间双向转换,并将这些信号连接到控制逻辑部分。 每个独立的内存单元都可以执行原子读写操作,以实现软件互斥操作(MUTEXes)。 每个矩阵都可以通过附加的行和/或列来防止缺陷。