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1. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

2. 发明授权

US08561044B2 Optimized code generation targeting a high locality software cache 失效
标题翻译：针对高位置软件缓存的优化代码生成
公开(公告)号：US08561044B2
公开(公告)日：2013-10-15
申请号：US12246602
申请日：2008-10-07
申请人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442
摘要： Mechanisms for optimized code generation targeting a high locality software cache are provided. Original computer code is parsed to identify memory references in the original computer code. Memory references are classified as either regular memory references or irregular memory references. Regular memory references are controlled by a high locality cache mechanism. Original computer code is transformed, by a compiler, to generate transformed computer code in which the regular memory references are grouped into one or more memory reference streams, each memory reference stream having a leading memory reference, a trailing memory reference, and one or more middle memory references. Transforming of the original computer code comprises inserting, into the original computer code, instructions to execute initialization, lookup, and cleanup operations associated with the leading memory reference and trailing memory reference in a different manner from initialization, lookup, and cleanup operations for the one or more middle memory references.
摘要翻译：提供了针对高位置软件缓存的优化代码生成机制。解析原始计算机代码以识别原始计算机代码中的内存引用。内存引用被分类为常规内存引用或不规则内存引用。常规内存引用由高位置缓存机制控制。原始计算机代码由编译器转换以生成转换的计算机代码，其中常规存储器引用被分组成一个或多个存储器参考流，每个存储器参考流具有前导存储器引用，尾随存储器引用和一个或多个中间内存引用。原始计算机代码的转换包括将原始计算机代码中的指令以不同于初始化，查找和清除操作的方式与前导存储器引用和尾随存储器引用相关联的执行初始化，查找和清除操作的指令进行插入或更多的中间内存引用。

3. 发明授权

US08468531B2 Method and apparatus for efficient inter-thread synchronization for helper threads 有权
标题翻译：帮助线程有效的线程间同步的方法和设备
公开(公告)号：US08468531B2
公开(公告)日：2013-06-18
申请号：US12787810
申请日：2010-05-26
申请人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
发明人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/4881 , G06F9/5022 , G06F9/52 , G06F9/542
摘要： A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.
摘要翻译：可以在具有多个硬件线程的多处理计算机系统中分配存储器位置中的每个硬件线程的监视器位，所述多个硬件线程共享存储器位置，并且所分配的监视器位中的每一个对应于多个硬件线程。可以为多个硬件线程中的每一个分配条件位，该条件位在多个硬件线程的每个上下文中被分配。响应于检测到被访问的存储器位置，确定是否设置了与存储器位置中的硬件线程相对应的监视位。响应于确定对应于硬件线程的监视位设置在存储器位置中，在硬件线程的上下文中设置与访问存储位置的线程相对应的条件位。

4. 发明授权

US08468508B2 Parallelization of irregular reductions via parallel building and exploitation of conflict-free units of work at runtime 失效
标题翻译：通过并行建设和运行时无冲突的工作单位利用不平等减少并行化
公开(公告)号：US08468508B2
公开(公告)日：2013-06-18
申请号：US12576717
申请日：2009-10-09
申请人： Alexandre E. Eichenberger , Yangchun Luo , John K. O'Brien , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , Yangchun Luo , John K. O'Brien , Xiaotong Zhuang
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： An optimizing compiler device, a method, a computer program product which are capable of performing parallelization of irregular reductions. The method for performing parallelization of irregular reductions includes receiving, at a compiler, a program and selecting, at compile time, at least one unit of work (UW) from the program, each UW configured to operate on at least one reduction operation, where at least one reduction operation in the UW operates on a reduction variable whose address is determinable when running the program at a run-time. At run time, for each successive current UW, a list of reduction operations accessed by that unit of work is recorded. Further, it is determined at run time whether reduction operations accessed by a current UW conflict with any reduction operations recorded as having been accessed by prior selected units of work, and assigning the unit of work as a conflict free unit of work (CFUW) when no conflicts are found. Finally, there is scheduled, for parallel run-time operation, at least two or more processing threads to process a respective the at least two or more assigned CFUWs.
摘要翻译：优化编译器装置，方法，计算机程序产品，其能够执行不规则减少的并行化。用于执行不规则减少的并行化的方法包括在编译器处接收程序并且在编译时选择来自程序的至少一个工作单元（UW），每个UW被配置为在至少一个简化操作上操作，其中 UW中的至少一个减少操作对于在运行时运行程序时地址是可确定的减法变量进行操作。在运行时，对于每个连续的当前UW，记录由该工作单元访问的减少操作的列表。此外，在运行时确定由目前的UW访问的减少操作是否与任何记录为由先前选择的工作单元访问的任何缩减操作相冲突，并且将工作单元分配为无冲突的工作单元（CFUW），当没有发现冲突。最后，对于并行运行时间操作，计划至少两个或更多个处理线程来处理相应的所述至少两个或更多个分配的CFUW。

5. 发明授权

US08453161B2 Method and apparatus for efficient helper thread state initialization using inter-thread register copy 有权
标题翻译：使用线程间寄存器复制的有效帮助线程状态初始化的方法和装置
公开(公告)号：US08453161B2
公开(公告)日：2013-05-28
申请号：US12787128
申请日：2010-05-25
申请人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
发明人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
IPC分类号： G06F13/00 , G06F12/00 , G06F9/30
CPC分类号： G06F9/544
摘要： This disclosure describes a method and system that may enable fast, hardware-assisted, producer-consumer style communication of values between threads. The method, in one aspect, uses a dedicated hardware buffer as an intermediary storage for transferring values from registers in one thread to registers in another thread. The method may provide a generic, programmable solution that can transfer any subset of register values between threads in any given order, where the source and target registers may or may not be correlated. The method also may allow for determinate access times, since it completely bypasses the memory hierarchy. Also, the method is designed to be lightweight, focusing on communication, and keeping synchronization facilities orthogonal to the communication mechanism. It may be used by a helper thread that performs data prefetching for an application thread, for example, to initialize the upward-exposed reads in the address computation slice of the helper thread code.
摘要翻译：本公开描述了一种方法和系统，其可以实现线程之间的值的快速，硬件辅助，生产者 - 消费者风格的通信。该方法在一个方面中使用专用硬件缓冲器作为用于将值从一个线程中的寄存器传送到另一线程中的寄存器的中间存储器。该方法可以提供通用的可编程解决方案，其可以以任何给定的顺序在线程之间传送寄存器值的任何子集，其中源寄存器和目标寄存器可以或可以不相关。该方法还可以允许确定的访问时间，因为它完全绕过存储器层次结构。此外，该方法被设计为轻量级，专注于通信，并保持与通信机制正交的同步设备。它可以由对应用程序线程执行数据预取的辅助线程使用，例如，初始化辅助线程代码的地址计算切片中的向上暴露的读取。

6. 发明授权

US08776034B2 Dynamically maintaining coherency within live ranges of direct buffers 失效
标题翻译：在直接缓冲区的生存范围内动态维护一致性
公开(公告)号：US08776034B2
公开(公告)日：2014-07-08
申请号：US13584356
申请日：2012-08-13
申请人： Tong Chen , John K. O'Brien , Tao Zhang
发明人： Tong Chen , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45 , G06T13/00 , H04L12/50
CPC分类号： G06F8/4442
摘要： Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.
摘要翻译：提供了减少数据处理系统中的一致性问题。要编译的源代码被接收和分析以识别包含存储器引用的多个循环中的至少一个循环。确定存储器引用是否是应该由直接缓冲器处理的全局存储器的访问。响应于指示存储器引用是对由直接缓冲器处理的全局存储器的访问，存储器引用被标记用于直接缓冲器转换。然后将直接缓冲区变换应用于存储器引用。

7. 发明授权

US08285670B2 Dynamically maintaining coherency within live ranges of direct buffers 失效
标题翻译：在直接缓冲区的生存范围内动态维护一致性
公开(公告)号：US08285670B2
公开(公告)日：2012-10-09
申请号：US12177507
申请日：2008-07-22
申请人： Tong Chen , John K. O'Brien , Tao Zhang
发明人： Tong Chen , John K. O'Brien , Tao Zhang
IPC分类号： G06F7/00
CPC分类号： G06F8/4442
摘要： Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.
摘要翻译：提供了减少数据处理系统中的一致性问题。要编译的源代码被接收和分析以识别包含存储器引用的多个循环中的至少一个循环。确定存储器引用是否是应该由直接缓冲器处理的全局存储器的访问。响应于指示存储器引用是对由直接缓冲器处理的全局存储器的访问，存储器引用被标记用于直接缓冲器转换。然后将直接缓冲区变换应用于存储器引用。

8. 发明授权

US08281295B2 Computer analysis and runtime coherency checking 失效
标题翻译：计算机分析和运行时一致性检查
公开(公告)号：US08281295B2
公开(公告)日：2012-10-02
申请号：US12125982
申请日：2008-05-23
申请人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
发明人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： Compiler analysis and runtime coherency checking for reducing coherency problems is provided. Source code is analyzed to identify at least one of a plurality of loops that contains a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by at least one of a software controlled cache or a direct buffer. A determination is made as to whether there is a data dependence between the memory reference and at least one reference from at least one of other direct buffers or other software controlled caches in response to an indication that the memory reference is an access to the global memory that should be handled by either the software controlled cache or the direct buffer. A direct buffer transformation is applied to the memory reference in response to a negative indication of the data dependence.
摘要翻译：提供了编译器分析和运行时相关性检查，以减少相关性问题。分析源代码以识别包含存储器引用的多个循环中的至少一个。确定存储器引用是否是对由软件控制的高速缓存或直接缓冲器中的至少一个来处理的全局存储器的访问。确定响应于存储器引用是对全局存储器的访问的指示，确定存储器引用与来自其他直接缓冲器或其他软件控制的高速缓存中的至少一个的至少一个引用之间是否存在数据依赖性应由软件控制的缓存或直接缓冲区来处理。响应于数据依赖性的负指示，将直接缓冲器变换应用于存储器引用。

9. 发明申请

US20110296421A1 METHOD AND APPARATUS FOR EFFICIENT INTER-THREAD SYNCHRONIZATION FOR HELPER THREADS 有权
标题翻译：用于帮助螺纹线的有效的线间同步的方法和装置
公开(公告)号：US20110296421A1
公开(公告)日：2011-12-01
申请号：US12787810
申请日：2010-05-26
申请人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
发明人： Michael K. Gschwind , John K. O'Brien , Valentina Salapura , Zehra N. Sura
IPC分类号： G06F9/52
CPC分类号： G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/4881 , G06F9/5022 , G06F9/52 , G06F9/542
摘要： A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the memory location, and each of the allocated monitor bit corresponding to one of the plurality of hardware threads. A condition bit may be allocated for each of the plurality of hardware threads, the condition bit being allocated in each context of the plurality of hardware threads. In response to detecting the memory location being accessed, it is determined whether a monitor bit corresponding to a hardware thread in the memory location is set. In response to determining that the monitor bit corresponding to a hardware thread is set in the memory location, a condition bit corresponding to a thread accessing the memory location is set in the hardware thread's context.
摘要翻译：可以在具有多个硬件线程的多处理计算机系统中分配存储器位置中的每个硬件线程的监视器位，所述多个硬件线程共享存储器位置，并且所分配的监视器位中的每一个对应于多个硬件线程。可以为多个硬件线程中的每一个分配条件位，该条件位在多个硬件线程的每个上下文中被分配。响应于检测到被访问的存储器位置，确定是否设置了与存储器位置中的硬件线程相对应的监视位。响应于确定对应于硬件线程的监视位设置在存储器位置中，在硬件线程的上下文中设置与访问存储位置的线程相对应的条件位。

10. 发明授权

US4881811A Remote color measurement device 失效
标题翻译：远程颜色测量装置
公开(公告)号：US4881811A
公开(公告)日：1989-11-21
申请号：US156471
申请日：1988-02-16
申请人： John K. O'Brien
发明人： John K. O'Brien
IPC分类号： A61C19/10 , G01J3/02 , G01J3/08 , G01J3/46 , G01N21/25
CPC分类号： G01J3/02 , A61C19/10 , G01J3/0218 , G01J3/0251 , G01J3/08 , G01J3/46 , G01J3/502 , G01J3/508 , G01J3/524 , G01N21/255 , G01N2021/4742 , G01N2021/4752 , G01N2201/065 , G01N2201/084
摘要： A probe, for use with a spectrophotometer, which senses the reflectance of a sample remote from the spectrophotometer. The probe includes a housing having a probe portion positionable proximate the sample, and an integrating chamber disposed within the probe housing and having a radiation input port, a sample port for passing diffused radiation to the sample and returning reflected radiation from the sample, a reference port, and an exit port to receive radiation reflected from the sample through the sample port. The probe further includes a guide for directing radiation to the radiation input port from a radiation source, and an element, responsive to the exit port and the reference port, for selectively conveying reflected radiation from the sample and the wall of the integrating chamber in the probe to the remote spectrophotometer.
摘要翻译：用于分光光度计的探针，用于检测远离分光光度计的样品的反射率。探针包括具有靠近样品定位的探针部分的壳体和设置在探针壳体内并具有辐射输入端口的积分室，用于将扩散的辐射传递到样品并返回来自样品的反射辐射的采样端口，参考端口和出口，用于接收从样品通过样品端口反射的辐射。探头还包括用于将辐射从辐射源引导到辐射输入端口的引导件，以及响应于出口和参考端口的元件，用于选择性地将反射的辐射从样品和积分室的壁传递到探头到远程分光光度计。

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