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1. 发明申请

US20200277781A1 HEAT-INSULATING STRUCTURAL MATERIAL, AND LOW TEMPERATURE AND ULTRA-LOW TEMPERATURE LIQUEFIED GAS CARRIER USING THE SAME 审中-公开
公开(公告)号：US20200277781A1
公开(公告)日：2020-09-03
申请号：US16646531
申请日：2018-09-05
申请人： Tae Young CHUNG
发明人： Tae Young CHUNG , Kong Ju PARK
IPC分类号： E04B1/80 , E04B1/76 , E04C2/292 , F17C3/08 , B32B15/095 , B32B3/06 , B32B7/08 , B32B3/08 , B32B15/18 , B32B27/40
摘要： The present invention relates to a heat-insulating structural material, which: firstly, can minimize or prevent a thermal bridge by improving the structure of the connection part of the heat-insulating structural material; secondly, improves insulation performance by arranging a vacuum insulation material inside the core layer of the heat-insulating structural material; and thirdly, increases structural stiffness by forming the core layer from a non-foaming polymer material having excellent structural performance, prevents gas from moving in or out of the vacuum insulation material through the air-tight adhesive structure of the core layer, and can improve fire protection performance so as not to be vulnerable to fire, and thus the present invention is universally applicable to fields requiring insulation ability and structural performance.

2. 发明申请

US20130248984A1 SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNELS AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130248984A1
公开(公告)日：2013-09-26
申请号：US13899911
申请日：2013-05-22
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L21/28123 , H01L21/76224 , H01L27/088 , H01L27/0886 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/0653 , H01L29/4238 , H01L29/66795 , H01L29/7802 , H01L29/7827 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

3. 发明申请

US20130193948A1 LOW POWER CIRCUIT FOR REDUCING LEAKAGE POWER USING NEGATIVE VOLTAGE 有权
标题翻译：用于降低泄漏电力的低功率电路使用负电压
公开(公告)号：US20130193948A1
公开(公告)日：2013-08-01
申请号：US13680040
申请日：2012-11-17
申请人： Jae Sup LEE , Seong Joong KIM , Bum Man KIM , Han-Kyu LEE , Dae-Chul JEONG , Tae Young CHUNG
发明人： Jae Sup LEE , Seong Joong KIM , Bum Man KIM , Han-Kyu LEE , Dae-Chul JEONG , Tae Young CHUNG
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , H03K17/063 , H03K2017/066
摘要： A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.
摘要翻译：提供了使用负电压降低漏电功率的电源电路。电源电路包括电流源，其包括包括栅极的晶体管。电源电路还包括连接到晶体管的栅极的电流源控制电路，并且被配置为如果电流源以工作模式工作，则向晶体管的栅极施加正电压，并将负电压施加到如果电流源要在非活动模式下工作，晶体管的栅极。

4. 发明授权

US08183113B2 Methods of forming recessed gate structures including blocking members, and methods of forming semiconductor devices having the recessed gate structures 失效
标题翻译：形成包括阻挡构件的凹陷栅极结构的方法，以及形成具有凹陷栅极结构的半导体器件的方法
公开(公告)号：US08183113B2
公开(公告)日：2012-05-22
申请号：US12784977
申请日：2010-05-21
申请人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
发明人： Yong-Sung Kim , Tae-Young Chung , Soo-Ho Shin , Eun-Cheol Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/4925 , H01L29/4933 , H01L29/4941 , H01L29/66621
摘要： A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.
摘要翻译：半导体器件中的凹陷栅极结构包括部分地埋在衬底中的栅电极，形成在栅极的掩埋部分中的阻挡构件以及形成在栅电极和衬底之间的栅极绝缘层。阻挡构件可以有效地防止栅极电极的掩埋部分中的空隙或接缝在随后的制造工艺中接触与沟道区域相邻的栅极绝缘层。因此，半导体器件可以具有规则的阈值电压，并且通过空隙或接缝的漏电流可以有效地降低。

5. 发明申请

US20120007175A1 Metal Oxide Semiconductor (MOS) Transistors Having a Recessed Gate Electrode 有权
标题翻译：具有嵌入式栅电极的金属氧化物半导体（MOS）晶体管
公开(公告)号：US20120007175A1
公开(公告)日：2012-01-12
申请号：US13236389
申请日：2011-09-19
申请人： Yong-Sung Kim , Tae-Young Chung
发明人： Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L29/51 , H01L29/66621
摘要： A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.
摘要翻译：金属氧化物半导体（MOS）包括设置在半导体衬底中以限定有源区的隔离层。源极区域和漏极区域设置在有源区域的两侧，使得从源极区域到漏极区域限定第一方向。通道凹槽设置在源区和漏区之间的有源区中。当从沿着与第一方向正交的第二方向截取的横截面视图观察时，通道凹部具有凸形表面。栅电极填充通道凹槽并沿第二方向跨过有源区。栅极绝缘层插入在栅电极和有源区之间。

6. 发明授权

US07920400B2 Semiconductor integrated circuit device and method of fabricating the semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的制造方法
公开(公告)号：US07920400B2
公开(公告)日：2011-04-05
申请号：US12055035
申请日：2008-03-25
申请人： Ju-Yong Lee , Sung-Ho Jang , Tae-Young Chung , Joon Han
发明人： Ju-Yong Lee , Sung-Ho Jang , Tae-Young Chung , Joon Han
IPC分类号： G11C5/06
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/10888 , H01L27/10891 , H01L29/66621
摘要： A semiconductor integrated circuit device having a 6F2 layout is provided. The semiconductor integrated circuit device includes a substrate; a plurality of unit active regions disposed in the substrate and extending in a first direction; first and second access transistors including first and second gate lines disposed on the substrate and extending across the unit active regions in a second direction forming an acute angle with the first direction; a first junction area disposed in the substrate between the first and second gate lines and second junction areas disposed on sides of the first and second gate lines where the first junction area is not disposed; a plurality of bitlines disposed on the substrate and extending in a third direction forming an acute angle with the first direction; and a plurality of bitline contacts directly connecting the first junction area and the bitlines.
摘要翻译：提供具有6F2布局的半导体集成电路器件。半导体集成电路器件包括衬底; 设置在所述基板中并沿第一方向延伸的多个单位活性区域; 第一和第二存取晶体管，包括设置在衬底上的第一和第二栅极线，并且沿与第一方向成锐角的第二方向延伸跨过单元有源区; 设置在第一和第二栅极线之间的衬底中的第一接合区域和设置在不设置第一接合区域的第一和第二栅极线的侧面上的第二接合区域; 多个位线设置在所述基板上并沿与所述第一方向成锐角的第三方向延伸; 以及直接连接第一连接区域和位线的多个位线触点。

7. 发明授权

US07790548B2 Methods of fabricating field effect transistors including recessed forked gate structures 有权
标题翻译：制造场效应晶体管的方法，包括凹进的分叉栅极结构
公开(公告)号：US07790548B2
公开(公告)日：2010-09-07
申请号：US11944819
申请日：2007-11-26
申请人： Bo-Young Song , Tae-Young Chung
发明人： Bo-Young Song , Tae-Young Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/66651 , H01L27/092 , H01L29/4236 , H01L29/66621 , H01L29/7834
摘要： A transistor includes substrate having an active region therein. The active region includes a recess therein having opposing sidewalls and a surface therebetween. A protrusion extends from the surface of the recess between the opposing sidewalls thereof. The transistor further includes a gate insulation layer on the protrusion in the recess, a gate electrode on the gate insulation layer in the recess, and source/drain regions in the active region on opposite sides of the gate electrode and adjacent to the opposing sidewalls of the recess. The gate electrode includes portions that extend into the recess between the protrusion and the opposing sidewalls of the recess. Related methods of fabrication are also discussed.
摘要翻译：晶体管包括其中具有有源区的衬底。活性区域包括其中具有相对的侧壁和它们之间的表面的凹部。突起从其相对侧壁之间的凹部的表面延伸。晶体管还包括在凹槽中的突起上的栅极绝缘层，凹槽中的栅极绝缘层上的栅极电极和位于栅电极的相对侧上的有源区域中的与源极/漏极区域相邻的相邻侧壁凹槽栅极电极包括延伸到突起和凹部的相对侧壁之间的凹部中的部分。还讨论了相关的制造方法。

8. 发明申请

US20100102384A1 METAL OXIDE SEMICONDUCTOR (MOS) TRANSISTORS HAVING A RECESSED GATE ELECTRODE 有权
标题翻译：带有电极的金属氧化物半导体（MOS）晶体管
公开(公告)号：US20100102384A1
公开(公告)日：2010-04-29
申请号：US12683089
申请日：2010-01-06
申请人： Yong-Sung Kim , Tae-Young Chung
发明人： Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L29/51 , H01L29/66621
摘要： A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.
摘要翻译：金属氧化物半导体（MOS）包括设置在半导体衬底中以限定有源区的隔离层。源极区域和漏极区域设置在有源区域的两侧，使得从源极区域到漏极区域限定第一方向。通道凹槽设置在源区和漏区之间的有源区中。当从沿着与第一方向正交的第二方向截取的横截面视图观察时，通道凹部具有凸形表面。栅电极填充通道凹槽并沿第二方向跨过有源区。栅极绝缘层插入在栅电极和有源区之间。

9. 发明授权

US07655522B2 Metal oxide semiconductor (MOS) transistor having a recessed gate electrode and methods of fabricating the same 有权
标题翻译：具有凹陷栅电极的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US07655522B2
公开(公告)日：2010-02-02
申请号：US11263434
申请日：2005-10-31
申请人： Yong-Sung Kim , Tae-Young Chung
发明人： Yong-Sung Kim , Tae-Young Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/51 , H01L29/66621
摘要： A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.
摘要翻译：金属氧化物半导体（MOS）包括设置在半导体衬底中以限定有源区的隔离层。源极区域和漏极区域设置在有源区域的两侧，使得从源极区域到漏极区域限定第一方向。通道凹槽设置在源区和漏区之间的有源区中。当从沿着与第一方向正交的第二方向截取的横截面视图观察时，通道凹部具有凸形表面。栅电极填充通道凹槽并沿第二方向跨过有源区。栅极绝缘层插入在栅电极和有源区之间。

10. 发明申请

US20090158079A1 Fault information processing system and method for vehicle 审中-公开
标题翻译：车辆故障信息处理系统及方法
公开(公告)号：US20090158079A1
公开(公告)日：2009-06-18
申请号：US12214751
申请日：2008-06-21
申请人： Tae Young Chung , Hyung Bin Ihm
发明人： Tae Young Chung , Hyung Bin Ihm
IPC分类号： G06F11/07 , G06F11/30
CPC分类号： G05B23/0264
摘要： The present invention relates to a fault information processing system and method for a vehicle, which can satisfy a short control cycle to thereby reduce the burden applied to the CPU and enables significant fault information (freeze frame) to be frozen. To this end, this invention features that the fault detection unit, the fault processing unit, the fault management unit having independent control cycles process all the faults occurred depending on a priority in such a fashion that fault-related data (freeze frame) is frozen immediately after the occurrence of a fault irrespective of the type of the occurred fault and the priority. Also, the fault management unit retrieves the occurred fault at an independent control cycle, combines the previously frozen fault-related data and the occurred fault, and stores corresponding fault information in a buffer unit.
摘要翻译：本发明涉及一种车辆的故障信息处理系统和方法，其可以满足短的控制周期，从而减轻施加到CPU的负担，并使重要的故障信息（冻结帧）被冻结。为此，本发明的特征在于故障检测单元，故障处理单元，具有独立控制周期的故障管理单元根据优先级来处理所有故障，使得故障相关数据（冻结帧）被冻结发生故障后立即发生，不管发生故障的类型和优先级。此外，故障管理单元在独立的控制周期检索发生的故障，组合先前冻结的故障相关数据和发生的故障，并将相应的故障信息存储在缓冲单元中。

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