专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10902113B2 Data processing 有权
公开(公告)号：US10902113B2
公开(公告)日：2021-01-26
申请号：US15793186
申请日：2017-10-25
申请人： ARM Limited
发明人： Guillaume Schon , Frederic Jean Denis Arsanto , Carlo Dario Fanara , Jocelyn François Orion Jaubert
IPC分类号： H04L29/06 , G06F21/55 , G06F9/30 , G06F21/75 , G06F11/30
摘要： Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.

2. 发明授权

US10445500B2 Reset attack detection 有权
公开(公告)号：US10445500B2
公开(公告)日：2019-10-15
申请号：US15635614
申请日：2017-06-28
申请人： ARM Limited
发明人： Guillaume Schon , Frederic Jean Denis Arsanto , Jocelyn François Orion Jaubert , Carlo Dario Fanara
IPC分类号： G06F21/56 , G06F3/06 , G06F21/62 , G06F21/78 , G06F21/57
摘要： An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.

3. 发明授权

US11593111B2 Apparatus and method for inhibiting instruction manipulation 有权
公开(公告)号：US11593111B2
公开(公告)日：2023-02-28
申请号：US16773059
申请日：2020-01-27
申请人： Arm Limited
发明人： Frederic Jean Denis Arsanto , Carlo Dario Fanara , Luca Scalabrino , Jean Sébastien Leroy
IPC分类号： G06F9/30 , G06F9/38
摘要： An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided. Scrambling circuitry is used to perform a scrambling function on each instruction using a secret scrambling key, such that the wire within the set of wires over which any given instruction bit is provided to the decoder circuitry is dependent on the secret scrambling key. The decode operation performed by the decoder circuitry is then adapted to incorporate a descrambling function using the secret scrambling key to reverse the effect of the scrambling function. As a result, independent of which wire any given instruction bit is provided on, the decode operation is arranged when decoding a given instruction to correctly interpret each instruction bit of that given instruction, based on knowledge of the instruction set, in order to determine from the value of each instruction bit the control signals to be issued to the execution circuitry in response to that given instruction.

4. 发明授权

US09646160B2 Apparatus and method for providing resilience to attacks on reset of the apparatus 有权
公开(公告)号：US09646160B2
公开(公告)日：2017-05-09
申请号：US14479688
申请日：2014-09-08
申请人： ARM LIMITED
发明人： Yohann Fred Arifidy Rabefarihy , Carlo Dario Fanara , Stephane Zonza , Jean-Baptiste Brelot
IPC分类号： G06F21/00 , G06F21/60 , G06F21/55
CPC分类号： G06F21/60 , G06F21/755 , G06F21/81
摘要： An apparatus and method are provided for enhancing resilience to attacks on reset of the apparatus. The apparatus comprises at least one storage element, and update circuitry that is configured to receive obscuring data, and which is responsive to a reset event to store in each of the at least one storage element a data value that is dependent on the current value of the obscuring data. For each such storage element, this ensures that the data value stored in that storage element is unpredictable following each reset event, thereby preventing the reproducibility of certain steps that would typically be taken by an attacker during an attack on the apparatus.

5. 发明授权

US11449642B2 Attack protection by power signature blurring 有权
公开(公告)号：US11449642B2
公开(公告)日：2022-09-20
申请号：US17012470
申请日：2020-09-04
申请人： Arm Limited
发明人： Carlo Dario Fanara , Frederic Jean Denis Arsanto , Luca Scalabrino
IPC分类号： G06F21/75
摘要： An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

6. 发明授权

US10540299B2 Resetting operating state holding element 有权
公开(公告)号：US10540299B2
公开(公告)日：2020-01-21
申请号：US15638524
申请日：2017-06-30
申请人： ARM LIMITED
发明人： Carlo Dario Fanara , Frederic Jean Denis Arsanto , Guillaume Schon , Jocelyn Francois Orion Jaubert
IPC分类号： G06F9/44 , G06F12/14 , G06F9/4401 , G06F9/24 , G06F1/24 , G06F9/30
摘要： An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

7. 发明申请

US20220075901A1 ATTACK PROTECTION BY POWER SIGNATURE BLURRING 有权
公开(公告)号：US20220075901A1
公开(公告)日：2022-03-10
申请号：US17012470
申请日：2020-09-04
申请人： Arm Limited
发明人： Carlo Dario Fanara , Frederic Jean Denis Arsanto , Luca Scalabrino
IPC分类号： G06F21/75
摘要： An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

8. 发明授权

US11263014B2 Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry 有权
公开(公告)号：US11263014B2
公开(公告)日：2022-03-01
申请号：US16531295
申请日：2019-08-05
申请人： Arm Limited
发明人： Frederic Claude Marie Piry , Thomas Christoper Grocutt , Simon John Craske , Carlo Dario Fanara , Jean Sébastien Leroy
IPC分类号： G06F9/30 , G06F9/38
摘要： Data processing apparatuses, methods of data processing, and non-transitory computer-readable media on which computer-readable code is stored defining logical configurations of processing devices are disclosed. In an apparatus, fetch circuitry retrieves a sequence of instructions and execution circuitry performs data processing operations with respect to data values in a set of registers. An auxiliary execution circuitry interface and a coprocessor interface to provide a connection to a coprocessor outside the apparatus are provided. Decoding circuitry generates control signals in dependence on the instructions of the sequence of instructions, wherein the decoding circuitry is responsive to instructions in a first subset of an instruction encoding space to generate the control signals to control the execution circuitry to perform the first data processing operations, and the decoding circuitry is responsive to instructions in a second subset of the instruction encoding space to generate the control signals in dependence on a configuration condition: to generate the control signals for the auxiliary execution circuitry interface when the configuration condition has a first state; and to generate the control signals for the coprocessor interface when the configuration condition has a second state.

9. 发明授权

US10572262B2 Register mapping of register specifiers to registers depending on a key value used for mapping at least two of the register specifiers 有权
公开(公告)号：US10572262B2
公开(公告)日：2020-02-25
申请号：US15651158
申请日：2017-07-17
申请人： ARM LIMITED
发明人： Jocelyn Francois Orion Jaubert , Frederic Jean Denis Arsanto , Guillaume Schon , Carlo Dario Fanara
IPC分类号： G06F9/38 , G06F9/30
摘要： An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式