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1. 发明授权

US08902690B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
标题翻译：需要单极编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

2. 发明授权

US08687398B2 Sense scheme for phase change material content addressable memory 有权
标题翻译：相变材料内容可寻址存储器的感应方案
公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译：一种用于感测内容可寻址存储器中匹配线的感测电路和方法。感测电路包括电反馈回路中电耦合到匹配线的反相器。逆变器包括匹配线的反相阈值。在预充电阶段期间，将匹配线充电至基本上第一电压阈值。当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

3. 发明申请

US20140052900A1 MEMORY CONTROLLER FOR MEMORY WITH MIXED CELL ARRAY AND METHOD OF CONTROLLING THE MEMORY 有权
公开(公告)号：US20140052900A1
公开(公告)日：2014-02-20
申请号：US13610830
申请日：2012-09-11
申请人： Bing Dai , Chung H. Lam , Jing Li
发明人： Bing Dai , Chung H. Lam , Jing Li
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F1/32 , G06F12/0246
摘要： A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

4. 发明申请

US20130314983A1 DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY 有权
公开(公告)号：US20130314983A1
公开(公告)日：2013-11-28
申请号：US13478932
申请日：2012-05-23
申请人： Chung H. Lam , Jing Li , Binquan Luan , Glenn J. Martyna , Dennis M. Newns
发明人： Chung H. Lam , Jing Li , Binquan Luan , Glenn J. Martyna , Dennis M. Newns
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C11/16 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/009 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit.

5. 发明申请

US20130039110A1 3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE 有权
标题翻译：使用双极性访问设备的双极存储器的3D架构
公开(公告)号：US20130039110A1
公开(公告)日：2013-02-14
申请号：US13209405
申请日：2011-08-14
申请人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
发明人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
IPC分类号： G11C5/02 , H01L21/02
CPC分类号： G11C13/00 , G11C5/02 , G11C7/00 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/224 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
摘要翻译：用于在两层半导体晶片上制造存储器件的存储器件和方法。示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造晶圆。

6. 发明授权

US09146852B2 Method of reducing system power with mixed cell memory array 有权
标题翻译：使用混合单元存储器阵列降低系统功率的方法
公开(公告)号：US09146852B2
公开(公告)日：2015-09-29
申请号：US13610834
申请日：2012-09-11
申请人： Bing Dai , Chung H. Lam , Jing Li
发明人： Bing Dai , Chung H. Lam , Jing Li
IPC分类号： G06F12/02
CPC分类号： G06F3/0625 , G06F1/3225 , G06F1/3275 , G06F3/0631 , G06F3/0653 , G06F3/0679 , G06F9/5016 , G06F12/02 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.
摘要翻译：一种存储系统，包括内存系统和减少内存系统功耗的方法。存储器系统包括可分配到多个处理器单元之一（例如处理器或处理器核）中的多个存储器单元。存储器控制器从处理器单元接收对存储器的请求，并从存储器向每个请求处理器单元分配足够的空间。分配的存储器可以包括存储每个单元的单个位的单个单元（SLC）存储器单元和存储每个单元多于一个位的其它存储器单元。因此，两个处理器单元可以被分配相同的存储器空间，而一个或更少个分配给另一个的单元的数量。

7. 发明申请

US20140092694A1 MULTI-BIT RESISTANCE MEASUREMENT 有权
标题翻译：多位电阻测量
公开(公告)号：US20140092694A1
公开(公告)日：2014-04-03
申请号：US13584120
申请日：2012-10-28
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/06 , G11C2207/068
摘要： An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.
摘要翻译：示例性实施例是用于确定存储器单元的二进制值的电路。该电路包括具有不同电容的并联电容器以选择性地与存储器单元耦合;以及控制器，被配置为将并联电容器迭代地充电至第一电压，直到所选择的并联电容器使第一电压衰减通过存储器单元为第一参考电压在预定时间范围内，基于所选择的并联电容器确定存储器单元的最高有效位的二进制值，在确定存储器单元的最高有效位的二进制值之后，将所选择的并联电容器充电至第二电压，并且基于通过存储器单元的所选择的并联电容器处的第二电压的衰减来确定存储器单元的最低有效位的二进制值。

8. 发明申请

US20140052901A1 MEMORY WITH MIXED CELL ARRAY AND SYSTEM INCLUDING THE MEMORY 有权
公开(公告)号：US20140052901A1
公开(公告)日：2014-02-20
申请号：US13610834
申请日：2012-09-11
申请人： Bing Dai , Chung H. Lam , Jing Li
发明人： Bing Dai , Chung H. Lam , Jing Li
IPC分类号： G06F12/02
CPC分类号： G06F3/0625 , G06F1/3225 , G06F1/3275 , G06F3/0631 , G06F3/0653 , G06F3/0679 , G06F9/5016 , G06F12/02 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

9. 发明申请

US20140022851A1 DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING 有权
标题翻译：用于双极二极管的三维存储器的解码方案需要单核编程
公开(公告)号：US20140022851A1
公开(公告)日：2014-01-23
申请号：US13584423
申请日：2012-08-13
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

10. 发明授权

US08560902B1 Writing scheme for phase change material-content addressable memory 有权
标题翻译：相变材料内容可寻址存储器的写入方案
公开(公告)号：US08560902B1
公开(公告)日：2013-10-15
申请号：US13587146
申请日：2012-08-16
申请人： Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C15/046 , G11C29/32 , G11C29/44
摘要： A method for programming a Phase Change Material-Content Addressable Memory (PCM-CAM). The method includes receiving a word to be written in a PCM-CAM. The word includes low bits represented by a low resistance state in the PCM-CAM and high bits represented by a high resistance state in the PCM-CAM. The method further includes repeatedly writing the low bits in memory cells of the PCM-CAM until the resistance of the memory cells are below a threshold value, and writing the high bits in memory cells of the PCM-CAM only once.
摘要翻译：一种用于编程相变材料内容可寻址存储器（PCM-CAM）的方法。该方法包括接收要写入PCM-CAM的单词。该字包括由PCM-CAM中的低电阻状态表示的低位和由PCM-CAM中的高电阻状态表示的高位。该方法还包括在PCM-CAM的存储单元中重复写低位，直到存储单元的电阻低于阈值，并将PCM-CAM的存储单元中的高位写入一次。

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